Senior Physical Design Engineer

MosChip®; Hyderabad; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

A leading semiconductor company in Hyderabad seeks an experienced engineer for ASIC Physical Design. This role involves floor planning, timing optimization, and mentoring Physical Design Engineers. The ideal candidate will have expertise in tools like Cadence, Synopsys, and strong scripting skills in PERL or TCL. Common duties include interfacing with front-end teams to resolve issues, ensuring timing closure on interfaces, and maintaining documentation. The company values communication and collaboration across teams.

Qualifications

• Extensive experience in ASIC Physical Design fundamentals.
• Ability to provide technical guidance and mentoring to team members.
• Strong background in timing optimization and analysis.
• Strong mentoring and cross-team collaboration capabilities.
• Interface with front-end ASIC teams to resolve design issues and drive closure.
• Timing closure on DDR2/DDR3/PCIE interfaces and related IPs.
• Proficiency with Cadence, Synopsys or Magma tool flows and Primetime/SI.
• Expertise in scripting languages such as PERL and TCL; good documentation skills.
• Excellent written and oral communication; ability to prioritize tasks.

Responsibilities

• Conduct top-level floor planning and PG planning.
• Facilitate timing closure on DDR2/DDR3/PCIE interfaces.
• Resolve issues with front-end ASIC teams.
• DRC/LVS checks and antenna checks; SI closure.
• Interface with front-end ASIC teams to resolve issues.
• Timing closure on DDR2/DDR3/PCIE interfaces.
• Work with Cadence or Synopsys or Magma physical design tool flows.
• Develop and maintain PERL/TCL scripts for flows and automation.
• Support strong physical verification and STA activities (Primetime/Primetime-SI).
• Communicate plans clearly and prioritize work across project teams.

Skills

ASIC Physical Design

Floor planning

Power Gating

Static Timing Analysis

Scripting languages (PERL, TCL)

Communication skills

Antenna checks

65nm / low power techniques

Voltage Islands/Power Gating/Substrate

Mentoring

Front-end interface

DDR2/DDR3/PCIE timing

Cadence tools

Synopsys tools

Magma tools

Primetime/SI

PERL scripting

TCL scripting

Communication skills

Team collaboration

Tools

Cadence

Synopsys

Magma

Primetime

Job description

• Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
• Worked on 65nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias.
• Provide technical guidance and mentoring to Physical Design Engineers.
• Interface with front-end ASIC teams to resolve issues.
• Timing closure on DDR2/DDR3/PCIE interfaces.
• Strong background of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
• Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
• Expertise in scripting languages such as PERL, TCL.
• Strong Physical Verification skill set.
• Static Timing Analysis in Primetime or Primetime-SI.
• Good written and oral communication skills. Ability to clearly document plans.
• Ability to interface with different teams and prioritize work based on project needs.