Physical Design Engineer

Broadcom; Maharashtra; On-site; INR 3,000,000 - 5,000,000; Full time

Job summary

Broadcom India Design is seeking an experienced engineer to lead backend digital design and physical implementation activities for advanced nodes. You will drive floorplanning, partitioning, placement, CTS/route, and STA closure while pushing automation and reusable flows.

Candidate should possess strong Tcl/Perl scripting skills, deep P&R knowledge across Cadence/Synopsys/Mentor tools, and collaborate across multi-functional teams in a fast-paced environment.

Qualifications

• MSEE/ MSCS with 10+ years of experience, or BSEE/BSCS with 12+ years.
• Deep understanding of backend digital design flow.
• Proficient in timing constraints, physical constraints.
• Proficient with backend EDA tools for SoC TOP.
• Proficiency in Tcl and Perl.
• Excellent analytical skills.
• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

Responsibilities

• Understand SoC top-down/bottom-up physical design integration in 5nm and lower technologies.
• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
• Implement timing and functional ECO.
• P&R, Extraction, Physical verification, work towards STA closure
• Build automation flows wherever needed/adapt to existing flows for re-use
• Must be proficient in any of the Cadence/Synopsys/Mentor EDA tools for P&R, PV, STA, ECO
• Needs to be automation savvy with high expertise in one of the programming languages used in the industry
• Clearly know requisites for executing his/her job and lead by example
• Bring tangible improvement in TAT with better quality

Skills

Backend design

Floorplanning

Timing analysis

Physical verification

Tcl & Perl scripting

Analytical skills

Cross-functional collaboration

Education

MSEE/ MSCS

BSEE/ BSCS

Tools

Genus

Innovus

Quantus

Tempus

DC

Star-RCXT

PrimeRail

Voltus

Redhawk

Job description

Job Description

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon.

Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification.

Responsibilities include, but not limited to:

• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
• Implement timing and functional ECO
• P&R, Extraction, Physical verification, work towards STA closure
• Build automation flows wherever needed/adapt to existing flows for re-use
• Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO
• Needs to be automation savvy with high expertise in one of the programming languages used in the industry
• Clearly know requisites for executing his/her job and lead by example
• Bring tangible improvement in TAT with better quality

Minimum Qualifications:

• MSEE/MSCS with 10+ years of experience, or BSEE/BSCS with 12+ years of experience
• A deep understanding of backend digital design flow
• Proficient in timing constraints, physical constraints
• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.
• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
• Proficiency in Tcl and Perl
• Excellent analytical skills
• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

R027249