Physical Design Engineer

Broadcom; Pune District; On-site; INR 400,000 - 700,000; Full time

Job summary

Broadcom is seeking an experienced EDA Layout Engineer to lead and execute backend physical design for cutting-edge 5nm and below technologies. You will drive timing and ECO flows, manage P&R, extraction, and PV tasks, and push STA closure while building reusable automation across teams.

Expected to contribute deep expertise in Genus/Innovus/Quantus/Tempus tools, TCL/Perl scripting, and cross-site collaboration. A strong backend design foundation and analytical mindset are essential.

Qualifications

• Backend flow and backend design experience required.
• Must understand timing and physical constraints.
• Hands-on experience with P&R/PV/STA tools across flows.
• Proficiency in Tcl and Perl scripting.
• Strong analytical skills and problem solving.
• Ability to collaborate across sites/time zones.

Responsibilities

• Understand SoC top-down/bottom-up physical design for 5nm and below.
• Deep knowledge of P&R flows and adapt internal flows.
• Implement timing and functional ECOs.
• Execute P&R, extraction, PV; drive STA closure.
• Build or adapt automation flows for reuse.
• Proficient with Cadence/Synopsys/Mentor EDA tools for P&R/PV/STA/ECO.
• Automation mindset using industry programming languages.

Skills

Backend digital design

Timing constraints

Physical constraints

EDA tools P&R/PV/STA

Tcl

Perl

Analytical skills

Team collaboration

Education

MSEE/MSCS with 10+ years

BSEE/BSCS with 12+ years

Tools

Genus

Innovus

Quantus

Tempus

DC/Star-RCXT/PT

PrimeRail/Voltus

Redhawk

Job description

Job Description

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification.

Responsibilities include, but not limited to:

• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
• Implement timing and functional ECO
• P&R, Extraction, Physical verification, work towards STA closure
• Build automation flows wherever needed/adapt to existing flows for re-use
• Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO
• Needs to be automation savvy with high expertise in one of the programming languages used in the industry
• Clearly know requisites for executing his/her job and lead by example
• Bring tangible improvement in TAT with better quality

Minimum Qualifications

• MSEE/MSCS with 10+ years of experience, or BSEE/BSCS with 12+ years of experience
• A deep understanding of backend digital design flow
• Proficient in timing constraints, physical constraints
• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.
• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
• Proficiency in Tcl and Perl
• Excellent analytical skills
• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.