Physical Design Engineer

UST; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

UST is seeking a skilled Physical Design Engineer to drive the ASIC/SoC physical design flow from synthesis to GDSII. You will ensure timing, power, and area targets are achieved while meeting project schedules in Bengaluru, India.

You will perform floorplanning, placement, CTS, routing, and physical verification, and collaborate with RTL, DFT, STA, and verification teams for design closure.

Qualifications

• Experience with ASIC/SoC physical design flow and RTL-to-GDSII flow.
• Strong understanding of timing, power, area, and QC targets.
• Proficiency with industry-standard EDA tools and scripts.

Responsibilities

• Drive physical design flow from synthesis to GDSII.
• Perform floorplanning, placement, CTS, routing, and signoff.
• Ensure timing, power, and area targets are met on schedule.
• Collaborate with RTL, DFT, STA, and verification teams.

Skills

ASIC/SoC flow

Digital design

Scripting

Team collaboration

Tools

Cadence Innovus

Synopsys ICC2

Tempus

Calibre

Job description

We are looking for a skilled Physical Design Engineer with experience in ASIC/SoC implementation from synthesis to GDSII. The candidate will be responsible for driving the physical design flow, ensuring timing, power, area, and quality targets are achieved while meeting project schedules.

Key Responsibilities:

• Floorplanning
• Power planning
• Placement
• Clock Tree Synthesis (CTS)
• Routing
• Physical verification
• Timing closure
• Analyze and fix setup/hold timing violations.
• Perform static timing analysis (STA) and timing signoff.
• Conduct IR drop, electromigration (EM), and power integrity analysis.
• Resolve DRC, LVS, and antenna violations.
• Collaborate with RTL, DFT, STA, and verification teams for design closure.
• Optimize design for performance, power, and area (PPA).
• Support tape-out activities and signoff requirements.
• Develop scripts for design automation and flow enhancement.

Required Skills:

• Strong understanding of ASIC/SoC physical design flow.
• Experience with industry-standard EDA tools such as:
• Cadence Innovus
• Synopsys ICC2
• Tempus
• Calibre
• Knowledge of:
• Timing constraints (SDC)
• STA concepts
• Multi-mode Multi-corner (MMMC)
• Low-power methodologies (UPF/CPF)
• Good understanding of semiconductor process technologies (7nm/10nm/16nm/28nm and above).