Physical Design Engineer

FiniteHR Consulting; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

FiniteHR Consulting is seeking experienced Physical Design engineers in Bengaluru, India, to join their team. Candidates must have 5-8 years of expertise and be proficient in handling Physical Design from Schematic to GDS II, using advanced EDA tools.

The role includes responsibilities from synthesis to Physical Verification closure. Ideal applicants have hands-on experience in technologies including 28nm and a strong grasp of VLSI processes.

Qualifications

• 5-8 years of experience in Physical Design.
• Experience with technology nodes like 28nm, 20nm, 14nm, 10nm.
• Experience in block/top level signoff and physical verification checks.

Responsibilities

• Responsible for Physical Design at Full Chip or block level.
• Involves Synthesis to PnR and Physical Verification closure.
• Utilize EDA tools for project delivery.

Skills

Netlist to GDS II handling

EDA tools knowledge

Floorplanning and routing

Physical verification expertise

VLSI process knowledge

Education

B. Tech. / M. Tech.

Tools

Synopsys

Cadence

Mentor

Job description

You will be part of a Physical Design team for projects with GHz freq range and cutting edge technologies.

You will be responsible for Physical Design at Full Chip or block level in technologies of 28nm/14nm.

You will be responsible for Synthesis to PnR and Physical Verification closure of SoC/sub-chips.

Desired Skills and Experience

• B. Tech. / M. Tech. with 5-8 years of experience in Physical Design
• Handled Netlist to GDS II at block level for multiple tape outs
• Hands‑on experience on technology nodes like 28nm, 20nm, 14nm, 10nm
• Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly experience with ICC, PTSI, Encounter, Nanoroute, Calibre, StarRC
• Hands‑on experience in floorplanning, placement optimizations, CTS and routing
• Hands‑on experience in block/top level signoff STA, physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks (IR/EM/Xtalk)
• Exposure in physical implementation of timing/functional ECO’s
• Good knowledge of VLSI process and device characteristics

Qualifications

• B. Tech. / M. Tech. with 5-8 years of experience in Physical Design

Additional Information

All your information will be kept confidential according to EEO guidelines.