Physical Design Engineer

Broadcom Inc.; Pune District; On-site; INR 4,000,000 - 7,500,000; Full time

Job summary

Broadcom Inc. in Pune seeks a senior backend physical design engineer with 10+ years of experience in layout, floorplanning, partitioning, placement, clock tree synthesis, routing and PV. You will drive timing closure, ECOs and automation, collaborating across multi-functional teams.

Candidate should demonstrate deep knowledge of backend digital design flow, EDA tools, and scripting in Tcl/Perl to improve turnaround time and quality. 5nm or lower node experience is preferred.

Qualifications

• Backend digital design knowledge is required.
• Must understand floorplanning, partitioning, placement and routing.
• Experience with timing constraints and ECOs is essential.

Responsibilities

• Lead floorplanning and placement for 5nm and below tech nodes.
• Execute timing closure and STA; drive ECOs and PV tasks.
• Develop automation flows to optimize turnaround time.

Skills

Layout experience

Backend digital design

Automation scripting

Cross-functional collaboration

Education

MSEE/MSCS

BSEE/BSCS

Tools

Genus/Innovus/Quantus/Tempus

DC/Star-RCXT/PT

PrimeRail/Voltus/Redhawk

Tcl

Perl

Job description

## **Job Description:**Job DescriptionIn this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification. Responsibilities include, but not limited to: • Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies • Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt. • Implement timing and functional ECO • P&R, Extraction, Physical verification, work towards STA closure • Build automation flows wherever needed/adapt to existing flows for re-use • Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO• Needs to be automation savvy with high expertise in one of the programming languages used in the industry • Clearly know requisites for executing his/her job and lead by example • Bring tangible improvement in TAT with better qualityMinimum Qualifications: • MSEE/MSCS with **10+** years of experience, or BSEE/BSCS with **12+** years of experience • A deep understanding of backend digital design flow • Proficient in timing constraints, physical constraints • Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP. • Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk • Proficiency in Tcl and Perl • Excellent analytical skills • Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone