Physical Design Lead Engineer

7Rays Semiconductors; Bengaluru; On-site; INR 1,600,000 - 2,300,000; Full time

Job summary

7Rays Semiconductors seeks a highly skilled Physical Design engineer 4 and above with hands-on expertise in Place & Route (PNR), Synthesis, and Signoff flows. Deep knowledge in timing closure, power analysis, and physical verification, with exposure to UPF low-power design methods, is essential.

Responsibilities include full-chip and block-level physical design, timing closure, signoff activities, DRC/LVS, IR/EM, and collaboration with RTL/DFT/backend teams to ensure design convergence and

Qualifications

• full-chip and block-level physical design including floorplanning, placement, CTS, routing, and optimization, across blocks and top-level
• timing closure under tight constraints using STA
• signoff workflows including PV, IR/EM checks and timing analysis
• VCLP (Voltage-aware checks) and LEC (Logical Equivalence Check) workflows
• exposure to low-power design techniques and UPF-based power intent
• collaboration with RTL/DFT/backend teams for design convergence and issue resolution

Responsibilities

• Execute full-chip and block-level physical design including floorplanning, placement, CTS, routing, and optimization
• Drive timing closure with a strong focus on Static Timing Analysis (STA)
• Manage signoff activities including STA (Setup/Hold closure), PV and IR/EM
• Physical Verification (DRC/LVS)
• IR Drop and EM analysis
• Perform logic synthesis ensuring timing, power, and area targets are met
• Conduct and analyze VCLP and LEC checks
• Collaborate with RTL, DFT, and backend teams for design convergence
• Debug and resolve timing, congestion, and power issues
• Implement and verify low-power intent using UPF

Skills

PNR

STA

Synthesis & Signoff

VCLP/LEC

UPF

Low-power design

Job description

We are seeking highly skilled Physical Design engineer 4 and above experincewith strong hands-on expertise in Place & Route (PNR), Synthesis, and Signoff flows. The ideal candidate will have deep knowledge of timing closure, power analysis, and physical verification, along with exposure to low-power design methodologies (UPF).

Key Responsibilities

• Execute full-chip and block-level physical design including floorplanning, placement, CTS, routing, and optimization
• Drive timing closure with a strong focus on Static Timing Analysis (STA)
• Manage signoff activities including:
• STA (Setup/Hold closure)
• Physical Verification (DRC/LVS)
• IR Drop and EM analysis
• Perform logic synthesis ensuring timing, power, and area targets are met
• Conduct and analyze VCLP (Voltage-aware checks) and LEC (Logical Equivalence Check)
• Collaborate with RTL, DFT, and backend teams for design convergence
• Debug and resolve timing, congestion, and power issues
• Implement and verify low-power intent using UPF

Mandatory Skills

• Strong hands-on experience in PNR (Place & Route) – MUST
• Expertise in Static Timing Analysis (STA) – HIGH PRIORITY
• Experience in Synthesis and Signoff flows (STA, PV, IR/EM)
• Knowledge of VCLP / LEC flows
• Exposure to low-power design techniques and UPF