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Digicomm Semiconductor INC in India is seeking engineers with experience or strong interest in memory compilers and layout optimization. The role emphasizes tackling routing congestion and physical verification while ensuring DRC/LVS/ERC/antenna/DFM checks are met.
Proficiency with Cadence and Mentor EDA tools, including VirtuosoXL, is highly valued. Ideal candidates demonstrate leadership, mentor junior engineers, and communicate proactively to drive quality and delivery in a fast-paced layout