Memory Layout Engineer

ACL Digital; Bengaluru; On-site; INR 400,000 - 700,000; Full time

Job summary

ACL Digital is seeking an experienced Memory Layout Engineer to lead the design and verification of memory compiler layouts, including memory blocks like arrays, decoders, and sense amplifiers. You will guide junior engineers, plan activities, and ensure timely delivery with high quality across India and Korea teams.

The role requires expertise in floor and power planning, layout verification (LVS/DRC), and strong communication within cross-functional teams.

Qualifications

• Experience in memory layout design for custom memory blocks (Array, decoders, sense amps).
• Strong leadership and delegation skills for multi-project environments.
• Proficiency with LVS/DRC and layout verification processes.

Responsibilities

• Lead memory compiler layout development and verification.
• Drive block-level layout delivery with quality and timelines.
• Mentor junior team members in sub-block layouts and reviews.

Skills

Memory layout design

Leadership

Team guidance

Problem solving

Layout verification

Tools

Cadence Virtuoso

Mentor Calibre

Parasitic Analysis

Job description

• Responsible for Memory Compiler layout development and verification.
• Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.
• Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
• Guide junior team-members in their execution of Sub block-level layouts & review their work.
• Contribute to effective project-management.
• Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.

Qualification/ Requirements:

• Should be well familiar with various levels of memory layouts from custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, decoders.
• Should have expertise in floor planning, power planning, block area estimation of memory designs or compliers.
• Should be able to perform leaf cell layout development and physical verification.
• Should have adequate knowledge of schematics, interface with circuit designer and CAD and process development team.
• Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Excellent in problem-solving skills in solving area, power, performance and physical verification of custom layout.
• Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.
• Should have leadership qualities and able to do multi-tasking as required.
• Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.
• Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.
• Knowledge of Skill coding and layout automation is a plus.