Memory Layout Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 1,500,000 - 3,200,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru, India, is seeking a memory layout engineer with 4–8 years of experience to design full-custom memory blocks such as SRAM and ROM. You will work on bit cells, decoders, and peripheral circuits, and perform floor planning, placement, routing, and verification.

You will collaborate with circuit and design engineers to implement optimized layouts, ensure DRC/LVS/ERC compliance, and support post-layout verification and tape-out activities for area,

Qualifications

• Memory Layout / Custom Layout experience required.
• 4–8 years in memory layout.
• Hands-on Cadence Virtuoso.
• Strong DRC/LVS/ERC and physical verification knowledge.
• Experience with Calibre or equivalent tools.
• Good CMOS devices knowledge, matching techniques and layout concepts.
• Experience with advanced technology nodes is a plus.

Responsibilities

• Develop full-custom memory layouts for SRAM, ROM and related blocks.
• Work on bit cells, row/column logic, sense amps, decoders, and drivers.
• Perform floor planning, placement, routing, matching and shielding.
• Ensure DRC/LVS/ERC and physical verification checks are met.
• Debug layout issues and support tape-out activities.

Skills

Memory Layout

Cadence Virtuoso

DRC/LVS/ERC

CMOS basics

Advanced nodes

Education

B.E./B.Tech in Electronics

Tools

Calibre

Job description

• Develop full-custom memory layouts for SRAM, ROM, Register File, and other memory-related blocks.
• Work on layout of bit cells, row/column logic, sense amplifiers, pre-charge circuits, decoders, drivers, and peripheral circuits.
• Perform floor planning, placement, routing, matching, shielding, and power planning.
• Ensure proper implementation of DRC, LVS, ERC and other physical verification checks.
• Debug and resolve layout and verification issues.
• Work closely with circuit/design engineers to understand schematics and implement optimized layouts.
• Support PEX and post-layout verification activities.
• Follow layout methodologies for area, performance, matching, reliability, and manufacturability.
• Support tape-out activities and ensure timely delivery of layout blocks.

Required Skills:

• Strong experience in Memory Layout / Custom Layout.
• 4-8 years of relevant experience in memory layout.
• Hands‑on experience with Cadence Virtuoso.
• Good understanding of DRC/LVS/ERC and physical verification.
• Experience with Calibre or equivalent verification tools.
• Good understanding of CMOS devices, matching techniques, common‑centroid layout, shielding, guard rings, and routing.
• Experience with advanced technology nodes is an added advantage.
• Ability to interpret schematics and work independently on layout implementation.

Preferred Experience:

• Advanced-node memory layout experience.
• Experience with TSMC / Samsung / GlobalFoundries technologies.
• Experience working on full-custom analog/mixed‑signal environments.