Senior Layout Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru seeks an experienced memory layout designer for SRAM/CAM/RF memories in cutting‑edge CMOS nodes. You will craft memory blocks, Row Decoder, IO, and control structures, with strong emphasis on floor planning and RC optimization.

The role requires hands‑on layout and verification, including LVS/DRC/ERC, and collaboration on compiler/integration tasks across memory architectures. Prior CMOs are preferred and knowledge of EM/IR is essential.

Qualifications

• Experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration) in CMOS processes.
• Strong knowledge of CMOS fabrication processes, foundries, and latest technology nodes.
• Proficient in industry-standard EDA tools such as Cadence Virtuoso and Mentor Graphics Calibre.

Responsibilities

• Layout design of SRAM/CAM/RF memories in advanced nodes (TSMC A14/2FF/3FF, Samsung SS8/SS2).
• Develop building blocks of memory architecture: Row Decoder, IO, and Control.
• Perform floor planning for placement, power distribution, and global routing; verify EM/IR.
• Compiler-level integration and final verification of compiler/custom memories.
• Work with memory compilers and ensure RC compliance for robust integration.

Skills

Problem solving

Communication

Memory layout design

Physical verification

Floor planning

Chip integration

RC requirements

Tools

Cadence Virtuoso

Mentor Graphics Calibre

ICV / DRC/LVS/ERC

Job description

• Layout Design of SRAM/CAM/RF custom/compiler memories in TSMC A14/2FF/3FF technologies or Samsung SS8/SS2 technologies.
• Responsibilities:
• Develop key building blocks of memory architecture, such as Row Decoder, IO, and Control.
• Skilled in pitched layout concepts and floor planning for Placement, Power, and Global Routing.
• Knowledge of EM/IR requirements.
• Compiler-level integration and final verification of Compiler/Custom memories.
• Strong knowledge of CMOS fabrication processes, foundries, and challenges in the latest technology nodes.
• Skills & Qualifications:
• Proficient in industry-standard EDA tools such as Cadence Virtuoso and Mentor Graphics Calibre.
• Strong problem-solving, logical reasoning, and communication skills.
• Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration) in CMOS processes.
• Extensive experience with physical verification tools such as Calibre and ICV (DRC, LVS, ERC, Antenna, and Softcheck Errors).
• Proficiency in floor planning, hierarchy layout, and chip integration.
• Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.
• Strong knowledge of memory layout topology; experience with memory compilers is preferred.