IP/SOC Verification Manager

BITSILICA; Hyderabad; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Bitsilica is seeking an experienced Design Verification Manager to lead verification activities for IP, subsystem, SoC and ASIC designs. The candidate will define verification methodologies, drive test plans, and mentor multiple verification teams to ensure on-time delivery.

You will develop scalable SystemVerilog/UVM based environments, oversee verification of interfaces, RAL, memory subsystems, and protocol compliance, and steer constrained-random, assertion-based, and coverage-driven

Qualifications

• 8+ years of hands-on verification experience in IP/SoC/ASIC.
• Strong leadership and project management capabilities.
• Proficiency with SystemVerilog and UVM methodologies.
• Experience building scalable verification environments.

Responsibilities

• Lead and manage Verification teams for IP, subsystem, and SoC/ASIC projects.
• Define verification methodologies, test plans, coverage goals and timelines.
• Develop scalable, reusable SystemVerilog/UVM verification environments.
• Verify subsystem interfaces, RAL, memory subsystems, and protocol compliance.
• Guide constrained-random, assertion-based, and coverage-driven verification.
• Ensure verification closure including coverage, assertions, regressions and debugging.
• Manage schedules, resources, priorities and risk across multiple programs.

Skills

SystemVerilog/UVM verification

SoC integration

AMBA protocols

Team leadership

Education

BE/BTech/ME/MTech in CS/Electronics/EE

Related field

Job description

We are seeking an experienced and results-driven Design Verification Manager to lead verification activities for complex IP, subsystem, SoC, and ASIC designs. The ideal candidate will possess strong technical expertise in SystemVerilog/UVM-based verification methodologies, SoC integration, AMBA protocols, and team leadership.

Key Responsibilities

• Lead and manage Design Verification teams for IP, subsystem, and SoC/ASIC verification projects.
• Define verification methodologies, strategies, test plans, coverage goals, and execution timelines.
• Drive development of scalable and reusable SystemVerilog/UVM-based verification environments.
• Oversee verification of subsystem interfaces, Register Abstraction Layer (RAL), memory subsystems, and protocol compliance.
• Guide teams in developing constrained-random, assertion-based, and coverage-driven verification environments.
• Ensure successful verification closure including functional coverage, code coverage, assertions, regressions, and debug.
• Manage project schedules, resource allocation, priorities, and risk mitigation across multiple concurrent programs.

Education & Experience

• BE/BTech/ME/MTech in Computer Science, Electronics, Electrical Engineering, or related field.
• 8+ years of hands-on experience in IP, SoC, or ASIC verification.