Lead Design Verification Engineer

Proxelera; Dadri; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

A leading tech company in Uttar Pradesh is hiring a SOC verification engineer to manage verification of complex SoCs. Ideal candidates will have over 8 years of hands-on experience in ASIC verification, strong expertise in UVM and System Verilog, and the ability to develop advanced testbench architectures. You will lead SOC-level verification, ensuring intricate component success including performance validation. This is a hands-on role, not suitable for purely managerial candidates.

Qualifications

• 8+ years of hands-on experience in ASIC verification.
• Expert in System Verilog, UVM, SVA, and constrained-random methodologies.
• Strong test planning and stimulus strategy skills.

Responsibilities

• Understand SOC architecture, Micro-architecture, and Design Specifications.
• Create and own SOC level verification plans.
• Develop modular, reusable UVM testbench architecture.

Skills

UVM

System Verilog

SOC verification

Testbench Architecture

Debug skills

Job description

We are hiring a hands‑on SOC verification engineer with strong UVM, and test Bench Architecture Own end‑to‑end verification of complex SoCs or large subsystems

What you’ll do

• Understand SOC architecture, Micro‑architecture and Design Specifications
• Create and own SOC level verification plans
• Develop modular, reusable UVM testbench architecture includes agents, scoreboard, Drivers, sequencers and Monitors
• Implement constrained random and direct test scenarios
• Lead SoC‑level verification: IP integration, coherency, low‑power modes, resets/boot, and performance validation
• Work closely with RTL, architecture, DFT, and firmware teams Support silicon bring‑up and pre‑/post‑silicon correlation

What we’re looking for

• 8+ years of hands‑on experience in ASIC verification
• Strong TB Architecture ownership — design, reuse strategy, scalability, and maintainability
• Multiple production ASIC tape outs with SoC or large subsystem ownership
• Expert in System Verilog, UVM, SVA, and constrained‑random methodologies
• Deep experience with AXI/ACE, DDR, PCIe, coherency, memory and interrupt fabrics Proven strength in test planning, stimulus strategy, checkers/scoreboards, and closure execution
• Excellent debug skills across simulation and silicon correlation

What won’t be considered

• FPGA/emulation-only experience does not count
• Pure management without recent hands‑on work