Lead - Design Verification (ASIC/SoC)

Alpha-Numero (A Quest Global Company); Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Alpha-Numero (A Quest Global Company) in Hyderabad seeks a Lead (Design Verification) with deep SoC verification experience to drive subsystem verification and coverage closure. You will develop DV test plans, build UVM environments, debug complex verification issues, and collaborate with architecture, RTL, and ATE teams to ensure robust silicon validation.

The role requires strong knowledge of ARM cores and AMBA protocols, SystemVerilog, and Cadence tools, with leadership and excellent

Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Engineering.
• 10–15 years of SoC/ASIC verification experience.
• Strong expertise in ARM architecture and AMBA protocols.
• Proficient in SystemVerilog and UVM.

Responsibilities

• Verify SoC subsystems and integrations.
• Develop DV test plans, test benches, and testcases.
• Build SystemVerilog/UVM verification environments.
• Perform functional verification and coverage closure.
• Debug simulation and integration issues.
• Work with AXI/AHB/APB-based subsystem verification.
• Collaborate with architecture, RTL, and ATE teams.
• Generate VCD/FSDB files for power analysis and testing.

Skills

SystemVerilog

UVM

ARM architecture

AMBA protocols

Cadence tools

Debugging

Team management

Communication

Problem solving

Education

Bachelor’s/Master’s in Electronics, Electrical, or Computer Engineering

Tools

Cadence tools

Job description

Role Overview

Looking for a Lead (Design Verification) with strong experience in SoC verification. The role involves subsystem verification, UVM-based environment development, protocol verification, debugging, and collaboration with design and architecture teams.

Key Responsibilities

• Verify SoC subsystems and integrations
• Develop DV test plans, test benches, and testcases
• Build SystemVerilog/UVM verification environments
• Perform functional verification and coverage closure
• Debug simulation and integration issues
• Work with AXI/AHB/APB-based subsystem verification
• Support gate-level simulation and low-power verification
• Collaborate with architecture, RTL, and ATE teams
• Generate VCD/FSDB files for power analysis and testing

Required Qualifications / Skills

• Bachelor s/Master s degree in Electronics, Electrical, or Computer Engineering
• 10-15 years of SoC/ASIC verification experience
• Strong expertise in ARM architecture and AMBA protocols
• Good experience in SystemVerilog and UVM
• Familiarity with Cadence simulation tools
• Strong debugging and verification skills
• Strong Communication, Interpersonal, Team Management, Problem Solving skills