IP/SOC Verification Manager

BITSILICA; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

BITSILICA is seeking an experienced Design Verification Manager to lead verification efforts for IP, subsystem, SoC, and ASIC designs in Bengaluru.

The ideal candidate will have deep expertise in SystemVerilog/UVM methodologies, AMBA protocols, and proven leadership to drive scalable verification environments and teams across multiple programs.

Qualifications

• BE/BTech/ME/MTech in Computer Science, Electronics, Electrical Engineering, or related field.
• 8+ years of hands-on IP/SoC/ASIC verification experience.

Responsibilities

• Lead and manage Design Verification teams for IP, subsystem, and SoC/ASIC verification projects.
• Define verification methodologies, strategies, test plans, coverage goals, and execution timelines.
• Drive development of scalable and reusable SystemVerilog/UVM-based verification environments.
• Oversee verification of subsystem interfaces, Register Abstraction Layer (RAL), memory subsystems, and protocol compliance.
• Guide teams in developing constrained-random, assertion-based, and coverage-driven verification environments.
• Ensure successful verification closure including functional coverage, code coverage, assertions, regressions, and debug.
• Manage project schedules, resource allocation, priorities, and risk mitigation across multiple concurrent programs.

Skills

SystemVerilog/UVM

Verification methodologies

SoC integration

AMBA protocols

Team leadership

Education

BE/BTech/ME/MTech in CS/EC/EE

Job description

We are seeking an experienced and results-driven Design Verification Manager to lead verification activities for complex IP, subsystem, SoC, and ASIC designs. The ideal candidate will possess strong technical expertise in SystemVerilog/UVM-based verification methodologies, SoC integration, AMBA protocols, and team leadership.

Key Responsibilities

• Lead and manage Design Verification teams for IP, subsystem, and SoC/ASIC verification projects.
• Define verification methodologies, strategies, test plans, coverage goals, and execution timelines.
• Drive development of scalable and reusable SystemVerilog/UVM-based verification environments.
• Oversee verification of subsystem interfaces, Register Abstraction Layer (RAL), memory subsystems, and protocol compliance.
• Guide teams in developing constrained-random, assertion-based, and coverage-driven verification environments.
• Ensure successful verification closure including functional coverage, code coverage, assertions, regressions, and debug.
• Manage project schedules, resource allocation, priorities, and risk mitigation across multiple concurrent programs.

Education & Experience

• BE/BTech/ME/MTech in Computer Science, Electronics, Electrical Engineering, or related field.
• 8+ years of hands-on experience in IP, SoC, or ASIC verification.