Lead Engineer - SOC Verification

Larsen & Toubro; Bengaluru; On-site; INR 2,800,000 - 5,600,000; Full time

Job summary

Larsen & Toubro in Bengaluru is seeking a Senior/Lead Engineer to drive SoC design verification. You will architect reusable testbenches and VIPs, and steer coverage across blocks and full-chip levels, ensuring quality and performance.

You will mentor junior engineers, collaborate with design and architecture teams, and apply SV/UVM, assertions, and formal methods to advance verification efficiency and reliability.

Qualifications

• 7+ years of ASIC/SoC verification with SV/UVM expertise.
• Experience building reusable verification environments and VIPs.
• Strong coverage-driven verification and code coverage experience.
• SV assertions and formal verification experience required.
• Full verification lifecycle from test plans to regression closure.
• Problem solving and analytical skills in a fast-paced setting.
• Bachelor’s or Master’s degree in Electronics/EE/CE or related field.

Responsibilities

• Architect and develop reusable testbenches and VIPs using SystemVerilog/UVM.
• Drive functional and code coverage closure across SoC blocks.
• Implement SV assertions and formal verification methods.
• Develop test plans and execute verification at block/chip levels.
• Lead debug and identify bottlenecks early in cycles.
• Mentor junior engineers on SV/UVM best practices.

Skills

SystemVerilog

UVM

VIP

Testbenches

Assertions

Formal verification

Coverage analysis

Mentoring

Debugging

Education

Bachelor's or Master's in Electronics/ Electrical Engineering / Computer Engineering

Tools

VIP Development

Formal Verification Tools

FPGA Prototyping

Job description

Position Overview

We are looking for a highly experienced Senior/Lead Engineer in SoC Design Verification to join our dynamic team and contribute to the development of cutting-edge SoC solutions.

We are looking for a highly experienced Senior/Lead Engineer in SoC Design Verification to join our dynamic team and contribute to the development of cutting-edge SoC solutions.

Key Responsibilities

• Architect and develop reusable testbenches and Verification IP (VIP) using SystemVerilog and UVM to create scalable verification environments from scratch.
• Drive coverage closure, ensuring thorough functional coverage and code coverage across all SoC components.
• Implement and manage SV assertions and coverage-driven verification strategies to validate designs effectively.
• Utilize formal verification methods and tools to verify complex blocks and subsystems, complementing simulation-based verification.
• Develop comprehensive test plans and ensure their execution at the block, subsystem, and full-chip levels.
• Lead debug activities and identify design and verification bottlenecks early in the development cycle.
• Mentor junior engineers on best practices for SV/UVM, reusable verification, assertions, and coverage analysis.
• Collaborate with design, architecture, and system-level teams to define and implement verification strategies that meet stringent quality and performance goals.
• Drive continuous improvement of verification methodologies and tools to enhance team efficiency and quality.

Requirements

• 7+ years of experience in ASIC/SoC verification, specializing in SystemVerilog (SV) and Universal Verification Methodology (UVM).
• Proven expertise in building reusable verification environments and VIP development from the ground up.
• Strong experience with coverage-driven verification, including functional and code coverage analysis and closure.
• Expertise in writing and debugging SV assertions and applying formal verification techniques.
• Hands-on experience with the full verification lifecycle, from test plan creation to regression analysis and closure.
• Strong problem-solving, debugging, and analytical skills in a fast-paced environment.
• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or related field.

Nice To Have

• Experience with Pre-Silicon Validation, including test environment setup and validation strategies.
• Proficiency in FPGA prototyping and hardware emulation to complement verification strategies.
• Familiarity with ARM-based SoC architectures and high-performance SoC designs for applications such as IP Cameras, automotive, or AI/ML.
• Knowledge of low-power verification and formal verification techniques.