Senior Design Verification Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru, India, is seeking a senior verification engineer with hands-on ASIC/SoC experience to lead complex verification of RTL and IP blocks.

You will develop SystemVerilog/UVM testbenches, define test plans, create functional coverage, and drive closure through collaboration with RTL and architecture teams. Strong debugging and assertion skills are essential to ensure robust verification of Ethernet-enabled designs.

Qualifications

• 5+ years of hands-on ASIC / SoC Design Verification experience.
• Strong experience with SystemVerilog & UVM.
• Hands-on verification experience in Ethernet.
• Develop and execute functional verification strategies for complex ASIC/SoC designs.
• Develop SystemVerilog/UVM testbenches, test scenarios and verification environments.
• Create test plans, test cases, functional coverage and assertions.
• Perform debugging and root‑cause analysis using simulation and waveform tools.
• Work closely with RTL Design, Architecture and SoC teams to identify and resolve design issues.
• Drive verification from test planning through coverage closure and sign‑off.
• Participate in IP, subsystem and SoC‑level verification.

Skills

ASIC verification

SoC verification

SystemVerilog

UVM

Testbench development

Functional coverage

Assertions

Debugging

RTL collaboration

Test planning

Job description

• 5+ years of hands‑on ASIC / SoC Design Verification experience
• Strong experience with SystemVerilog & UVM
• Hands‑on verification experience in any one or more of the following protocols:
• Ethernet
• Develop and execute functional verification strategies for complex ASIC/SoC designs.
• Develop SystemVerilog/UVM testbenches, test scenarios and verification environments.
• Create test plans, test cases, functional coverage and assertions.
• Perform debugging and root‑cause analysis using simulation and waveform tools.
• Work closely with RTL Design, Architecture and SoC teams to identify and resolve design issues.
• Drive verification from test planning through coverage closure and sign‑off.
• Participate in IP, subsystem and SoC‑level verification.