IO and Mixed Signal Layout Design Engineer

Broadcom; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

Broadcom Bengaluru is seeking a senior Layout Engineer to design I/O libraries and analog IP layouts in planar and FinFET tech. You will drive floorplanning, ensure routing efficiency, and verify layouts end-to-end across global teams.

The role requires 5–8 years of experience with strong CAD tool proficiency and a track record in physical design, ESD/Latch-up concepts, and LEF/PnR workflows. Join a collaborative team with exposure to advanced process nodes.

Qualifications

• B.Tech/M.Tech in Electronics/Electrical engineering with 5–8 years of experience.
• Hands-on experience in I/O Library and Analog Mixed-signal IP development and verification.
• Solid understanding of planar and FinFET layouts and process technology.
• Knowledge of IO frame and pitch requirements, power planning, and IO segment rules.
• Familiar with DRC/LVS/ERC/DFM and related verifications.
• Experience with LEF generation and physical design flow.

Responsibilities

• Design full custom layouts of I/O libraries and Analog Mixed Signal IPs in planar and FinFET technologies.
• Drive critical floor-planning decisions to optimize placement and routing.
• Perform comprehensive layout verification to ensure quality and compliance.
• Own end-to-end deliverables within schedule and budget.
• Adapt quickly to new methodologies and collaborate across sites.

Skills

IO Library

Analog mixed-signal IP development

Planar/FinFET layouts

Full-chip concepts

ESD and latch-up principles

DRC/LVS/ERC/DFM

LEF generation and PnR

Script programming

SKILL scripting

AI in layout

Education

B.Tech/M.Tech in Electronics/Electrical engineering

Tools

Cadence Virtuoso Layout Suite

Siemens CALIBRE

Job description

Job Description:

• Design full custom layouts of I/O libraries and Analog Mixed Signal IP's in planar and FinFET technologies.
• Drive critical floor-planning decisions to ensure optimal placement and routing that meets design requirements and performance metric.
• Perform comprehensive layout verification to ensure high quality and compliance
• Complete ownership from end to end deliverables with quality within the schedule.
• Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the teams across all sites.

Skills and Qualifications Required:

• B.Tech/M.Tech in Electronics/Electrical engineering with 5-8 years of experience
• Hands-on experience in I/O Library and Analog Mixed-signal IP development and verification
• Solid understanding of Planar and FinFET layouts and process technology
• Good understanding of Full-chip concepts, IO frame and pitch requirements, power planning, IO segment rules and requirements
• In-Depth knowledge of ESD and Latch-up principles for I/O and Analog layouts
• Proficiency in using Cadence Virtuoso Layout suite and Siemens CALIBRE verification tools.
• Expertise in Layout verifications and debugging: DRC/LVS/ANT/ERC/DFM, LPE, PERC, EM and IR etc
• Familiar with the Physical Design flow: LEF generation and PnR
• Knowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus.
• Excellent written and verbal communication skills to collaborate with circuit designers and teams across all sites
• Able to lead, train junior engineers, and manage projects effectively.
• Self-motivated, capable of working independently, and a strong collaborative team player.