Analog Layout Engineer

Cyient; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Cyient Semiconductor is seeking an experienced Analog Layout Engineer to join our growing Analog & Mixed-Signal design team in Bengaluru. The role focuses on custom analog layout development, layout optimization for IPs, and close collaboration with circuit designers to meet performance and power targets.

The ideal candidate has 3–5 years of hands-on analog layout experience, with exposure to Non-FinFET process nodes (180nm–40nm) and Cadence Virtuoso tools.

Qualifications

• 3–5 years hands-on analog layout design.
• Experience with Non-FinFET processes (180nm to 40nm).
• Experience in Analog/Mixed-Signal layouts and PMIC layouts.
• Knowledge of matching, noise coupling, electromigration and ESD concepts.

Responsibilities

• Develop high-quality analog layouts for blocks such as Bandgap References, LDOs, Charge Pumps, PMIC blocks.
• Perform floorplanning and layout implementation with matching, symmetry, noise isolation and reliability.
• Execute and debug physical verification checks including DRC, LVS, ERCAntenna checks and density checks.
• Collaborate with circuit designers to achieve performance, area and power targets and assist extraction improvements.

Skills

Analog Layout

PMIC Layouts

Layout Matching

Noise Coupling

EM and ESD concepts

Cadence Virtuoso

Education

B.E./B.Tech/M.E./M.Tech in Electronics, VLSI, Microelectronics, Electrical Engineering, or related field

Tools

Cadence Virtuoso Layout Suite

Calibre DRC/LVS

Parasitic Extraction Tools

Job description

Key Responsibilities

• Develop high-quality custom analog layouts for blocks such as:
  • Bandgap References
  • LDOs
  • Charge Pumps
  • PLLs
  • Data Converters (ADC/DAC)
  • Current Mirrors
  • Op-Amps
  • Comparators
  • PMIC Blocks
• Perform floorplanning and layout implementation while ensuring optimal matching, symmetry, noise isolation, and reliability.
• Execute and debug physical verification checks including:
  • DRC
  • LVS
  • ERCAntenna Checks
  • Density Checks
• Collaborate closely with circuit designers to achieve performance, area, and power targets.
• Understand parasitic effects and work on extraction-related layout improvements.
• Implement layout techniques such as:
  • Common Centroid
  • Interdigitation
  • Shielding
  • Guard Rings
  • Device Matching
  • ESD-Aware Layout Practices
• Support tape-out activities and resolve foundry sign-off issues.
• Work with cross-functional teams to ensure successful project execution.

Required Skills & Experience

Technical Skills

• 3-5 years of hands-on experience in Analog Layout Design.
• Strong experience in Non-FinFET process technologies such as:
  • 180nm
  • 130nm
  • 90nm
  • 65nm
  • 40nm
• Experience in Analog/Mixed Signal layouts and PMIC layouts.
• Strong understanding of:
  • Matching techniques
  • Noise coupling
  • Electromigration
  • Latch-up prevention
  • ESD concepts
• Hands-on experience with:
  • Cadence Virtuoso Layout Suite
  • Calibre DRC/LVS
  • Parasitic Extraction Tools
• Good understanding of semiconductor fabrication processes and device structures.

Preferred Qualifications

• Experience in PMIC, Automotive, Industrial, Consumer Electronics, or Power Management products.
• Exposure to complete chip tape-out cycle.
• Knowledge of reliability and yield optimization techniques.
• Experience working with TSMC, GlobalFoundries, UMC, or similar foundry technologies.

Educational Qualification

• B.E./B.Tech/M.E./M.Tech in Electronics, VLSI, Microelectronics, Electrical Engineering, or related field.

Roles and Responsibilities

About the Role Cyient Semiconductor is looking for highly motivated and skilled Analog Layout Engineers with strong experience in Non-FinFET technologies to join our growing Analog & Mixed-Signal design team. The ideal candidate should possess hands‑on expertise in custom analog layout development, physical verification, and layout optimization for advanced analog and mixed-signal IPs.