Technical Lead I - VLSI IOL

UST; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

UST is seeking an IO Layout Engineer with 4–10 years of hands-on experience in IO layout, including GPIO, analog IOs, high-speed IOs and pad rings. The role emphasizes TSMC 5nm layout experience, Totem EMIR and Calibre PV checks, and solid understanding of layout fundamentals.

You'll collaborate with design teams to meet constraints, perform sign-off PV checks, and contribute to top-level floorplan work and IP layout under senior guidance.

Qualifications

• Bachelor's/Master's in Electronics & Communication or Electrical Engineering required.
• 4–10 years of hands-on IO layout experience is essential.
• Experience with IO blocks: GPIO, Analog IOs, High Speed IOs and pad rings.

Responsibilities

• Work on IO layout for SanDisk ASIC controllers under guidance of senior team members.
• Collaborate with designers to understand constraints and deliver efficient layouts.

Skills

IO Layout

Analog IO

High-Speed IO

Top-level Floorplan

IP Layout

Sign Off PV

Signal Integrity

LVS

Education

Bachelor's/Master's in Electronics & Communication or Electrical Engineering

Tools

Cadence Virtuoso

Calibre

StarRC Extraction

Totem EMIR

Job description

Role Description

Job title: - IO Layout Engineer Qualification/Requirements Bachelors/master’s degree in Electronics & Communication/Electrical engineering. Working experience (4 to 10 years) in IO layout. Hands-on experience in layout design of IO blocks such as GPIO, Analog IOs, High Speed IOs and Pad ring. Experience in high-speed, low-power mixed-signal IP’s is a plus. Experience in TSMC 5nm layout (or below) using Virtuoso EXL features. Must have expertise on Totem EMIR & Self-heating effects, Star RC extraction, and Calibre PV checks (DRC, LVS, Antenna, ERC, PERC etc.). Good Understanding of layout fundamentals (Matching, EM, ESD, Latch up, coupling, crosstalk etc.). Experience in top-level floorplan, hierarchical layout methodologies. Good Verbal and written communication skills. Candidates having only memory/Standard Cell layout experience are not relevant to this requirement.

Role and Responsibilities: Will work on IO layout for SanDisk ASIC controllers under guidance of senior team members. Collaborate closely with designers to understand the design constraints and create quality layout in efficient manner. Manage all the Sign Off PV & quality checks on an IP layout.

Skills

• Analog Layout
• Analog Mixed-Signal
• GPIO
• TSMC
• Cadence Virtuoso
• Calibre
• Signal Integrity
• LVS