DFT Engineer

HR Central; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

HR Central is seeking a DFT Engineer in Bangalore to contribute to test access and scan design for complex SoCs. The role emphasizes BSCAN/MBIST/ATPG understanding, GUI-based debugging, and collaboration across customer and internal teams.

Candidates should have hands-on experience with Cadence, Tessent, or Synopsys tools and a strong grasp of timing simulations and fault models. On-site in Bangalore with growth opportunities in post-silicon activities.

Qualifications

• Understanding of BSCAN, MBIST, SCAN, ATPG and simulation concepts.
• Experience in MBIST insertion, scan insertion, ATPG pattern generation and simulations.
• Exposure to MBIST and BSCAN simulations using Cadence, Tessent or Synopsys tools.
• Knowledge of zero delay and SDF timing simulations is a plus.
• Strong debugging skills using GUI simulators (VCS, NCSim, Xcelium).
• Experience with fault models like stuck-at, TDF, IDDQ and scan test coverage improvement techniques.
• SoC level DFT experience including OCC/OPCG insertion, EDT/Compression logic, and clock module handling for scan.

Responsibilities

• Understand and implement BSCAN/MBIST/ATPG/SCAN concepts for DFT.
• Perform MBIST insertion, scan insertion, ATPG pattern generation and simulations.
• Run MBIST and BSCAN simulations using Cadence/Siemens Tessent/Synopsys tools.
• Conduct zero delay and SDF timing simulations as needed.
• Debug using GUI tools like VCS, NCSim or Xcelium.
• Work on fault models (stuck-at, TDF, IDDQ) and improve scan test coverage.
• Contribute to OCC/OPCG insertion, EDT/Compression logic, and clock handling for scan and post-silicon activities.
• Provide test mode timing constraints to STA and PD teams.
• Collaborate with cross-functional and customer teams; mentor DFT engineers.

Skills

BSCAN

MBIST

ATPG concepts

Simulation concepts

Cross-functional collaboration

Tools

Cadence

Siemens Tessent

Synopsys

VCS

NCSim

Xcelium

Job description

DFT Engineer

Bangalore, India

Experience: 3-15 Years

Role

• The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.
• Should have experience in atleast one : MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.
• Good to have worked on zero delay as well as SDF Timing Simulations.
• Should have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
• Good to have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.
• Candidate should have worked in SoC level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and /or production activities with exposure to Tester debug usings shmoo plots and graphs.
• The candidate should have experience of providing test mode timing constraints to STA and PD teams.
• Good communication skills and debugging skills are a must to have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.