Dft Design Engineer

7rays Semiconductors; Hyderabad, Bengaluru, Greater Noida; On-site; INR 400,000 - 800,000; Full time

Job summary

7rays Semiconductors in Hyderabad seeks a DFT engineer to work beyond RTL/DFT implementation with exposure to real silicon. You will engage in MBIST insertion, scan insertion, ATPG pattern generation and simulations, and timing/STA collaborations.

The role requires hands-on experience with tests like BSCAN/MBIST, zero delay and SDF timing simulations, and debugging with VCS/NCSim/Xcelium. Strong cross-functional communication is essential.

Qualifications

• Understanding of BSCAN, MBIST, SCAN, ATPG, and Simulation concepts.
• Hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using Cadence/Tessent/Synopsys.

Responsibilities

• Understand BSCAN, MBIST, SCAN, ATPG concepts.
• Hands-on MBIST insertion, Scan Insertion, ATPG pattern generation and simulations.
• Work with MBIST and BSCAN simulations using Cadence/Tessent/Synopsys.
• Perform zero delay and SDF Timing Simulations.
• Debug using GUI modes of industry standard simulators (VCS, NCSim, Xcelium).
• Work on fault models like stuck-at, TDF, IDDQ and improve scan test coverage.
• Involve OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan and post-silicon bring-up.
• Provide test mode timing constraints to STA and PD teams.
• Perl/Tcl scripting is a plus.
• Strong communication and mentoring of DFT Engineers.

Skills

MBIST

BSCAN

SCAN

ATPG

IEEE 1687

IJTAG

SSN

DFT Repair

Yield Improvement

Silicon Bring-up

ATE Debug

Tools

Tessent

Cadence

Synopsys

VCS

NCSim

Xcelium

Job description

About the role:

We're looking for DFT engineers who want to work beyond just RTL/DFT implementation and get hands‑on exposure to real silicon.

• SCAN, MBIST & ATPG
• IJTAG / IEEE 1687 & Streaming Scan (SSN)
• DFT Repair & Yield Improvement
• Silicon Bring‑up & ATE Debug
• Hands‑on with Tessent, Synopsys & Cadence
• Advanced technology nodes: 2nm, 3nm, 6nm, 4nm and below

Job description:

• The candidate is expected to have a clear understanding of BSCAN, MBIST, SCAN, ATPG, and Simulation concepts.

• Must be hands‑on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry‑standard tools of Cadence/Siemens Tessent/Synopsys.

• Candidate must have worked on zero delay as well as SDF Timing Simulations

• Must have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.

• The candidate should have worked on fault models like stuck‑at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.

• The candidate should have worked in SoC‑level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post‑silicon bring‑up and /or production activities with exposure to Tester debug usings shmoo plots and graphs.

• The candidate should have experience of providing test mode timing constraints to STA and PD teams.

• Additional knowledge of perl/tcl scripting will be an advantage.
• Good communication skills and debugging skills are a must to have qualities for this role as it involves cross‑functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.