DFT Engineer

Cortex Consultants LLC; Chennai District; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Cortex Consultants LLC is seeking a seasoned DFT Engineer in Chennai, India, specializing in Scan DFT implementation for complex SoC/ASIC designs. The ideal candidate will have 5+ years of hands-on experience with Scan insertion, ATPG, and coverage analysis.

The role involves working closely with RTL, PD, and validation teams, ensuring quality and compliance in DFT implementations. Strong knowledge of DFT tools like Tessent and Synopsys DFT Compiler is crucial.

Qualifications

• 5+ years of experience in DFT Scan.
• Strong hands-on experience in Scan insertion, Scan stitching, ATPG, and Scan compression.
• Good knowledge of stuck-at, transition fault, and coverage analysis.

Responsibilities

• Work on DFT Scan implementation for SoC / ASIC designs.
• Handle Scan insertion, Scan stitching, Scan compression, and ATPG pattern generation.
• Perform fault coverage analysis and improve test coverage.
• Debug Scan / ATPG / pattern simulation issues.
• Work closely with RTL, PD, STA, and Validation teams for DFT closure.
• Support pattern verification, pattern bring-up, and silicon debug activities.
• Ensure DFT implementation meets quality and test requirements.

Skills

Scan insertion

DFT implementation

ATPG

Scan compression

Coverage analysis

Pattern validation

Tools

Tessent

Modus

Synopsys DFT Compiler

TetraMAX

Job description

Overview

We are looking for an experienced DFT Engineer with 5+ years of experience in Scan DFT implementation and validation for complex SoC/ASIC designs. The ideal candidate should have strong hands-on expertise in Scan insertion, Scan ATPG, compression, coverage analysis, and pattern validation.

Job Title: DFT Engineer SCAN

Experience: 5+ Years

Location: Chennai

Responsibilities

• Work on DFT Scan implementation for SoC / ASIC designs
• Handle Scan insertion, Scan stitching, Scan compression, and ATPG pattern generation
• Perform fault coverage analysis and improve test coverage
• Debug Scan / ATPG / pattern simulation issues
• Work closely with RTL, PD, STA, and Validation teams for DFT closure
• Support pattern verification, pattern bring-up, and silicon debug activities
• Ensure DFT implementation meets quality and test requirements

Qualifications

• 5+ years of experience in DFT Scan
• Strong hands-on experience in Scan insertion, Scan stitching, ATPG, Scan compression
• Good knowledge of stuck-at, transition fault, and coverage analysis
• Experience in pattern simulation and debug
• Familiarity with DFT tools like Tessent / Modus / Synopsys DFT Compiler / TetraMAX
• Good understanding of ASIC/SoC design flow
• Ability to work with cross-functional teams for DFT closure