08303 DFT Engineer (Senior/Manager)

Cephas Consultancy Services Private Limited; Bengaluru; Sur place; INR 900 000 - 1 300 000; Plein temps

Résumé du poste

Cephas Consultancy Services Private Limited is seeking an experienced DFT engineer for a full-time role in Bengaluru. The candidate should have deep understanding of BSCAN, MBIST, SCAN, ATPG and related simulation concepts, with hands-on experience in MBIST insertion, scan insertion, ATPG pattern generation and simulations.

Exposure to MBIST/BSCAN simulations using Cadence, Siemens Tessent, or Synopsys tools is required, along with knowledge of zero-delay and SDF timing simulations.

Qualifications

• Clear understanding of BSCAN, MBIST, SCAN, ATPG and Simulation concepts.
• Experience in MBIST insertion, Scan Insertion, ATPG pattern generation and simulations.
• Exposure to MBIST/BSCAN simulations using Cadence/Tessent/Synopsys tools.
• Good to have zero-delay timing and SDF timing simulations.
• Strong GUI debugging skills with VCS, NCSim or Xcelium.

Responsabilités

• Lead DFT activities for SOCs, including OCC/OPCG insertion and clock handling for scan purposes.
• Provide test mode timing constraints to STA and PD teams.
• Support post-silicon bring-up and production activities with tester debugging insights.

Connaissances

BSCAN/SCAN concepts

ATPG patterns

MBIST/MBIST insertion

OCC/OPCG insertion

Clock domain handling for scan

Post-silicon bring-up

STA/PD constraints

GUI debugging (VCS/NCSim/Xcelium)

Outils

Cadence Tessent

Siemens Tessent

Synopsys

VCS

NCSim

Xcelium

Description du poste

About this position

Positions:20 Full Time
Experience
3 - 15 Years

Experience: 3-15 Years

Role -

• The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.
• Should have experience in atleast one : MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.
• Good to have worked on zero delay as well as SDF Timing Simulations.
• Should have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
• Good to have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.
• Candidate should have worked in SoC level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and /or production activities with exposure to Tester debug usings shmoo plots and graphs.
• The candidate should have experience of providing test mode timing constraints to STA and PD teams.

Good communication skills and debugging skills are a must to have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.