DFT Engineer - Bengaluru

HR Central; Bengaluru; Hybrid; INR 1,800,000 - 3,000,000; Full time

Job summary

HR Central in Bengaluru is seeking an experienced DFT Engineer to design and implement DFT architectures for complex SoCs across advanced technology nodes. You will handle architecture, insertion, ATPG pattern generation, and silicon bring-up with cross-functional teams.

The role requires hands-on experience with BSCAN/MBIST/SCAN/ATPG and strong familiarity with industry tools (Tessent, Synopsys, Cadence). You will mentor junior DFT engineers and support post-silicon activities.

Qualifications

• Deep understanding of BSCAN, MBIST, SCAN and ATPG.
• Hands-on experience with industry-standard toolchains.
• Familiarity with simulation-based verification and timing closure.

Responsibilities

• Develop SoC-level DFT architecture including OCC/OPCG and EDT/Compression logic.
• Perform MBIST and scan insertion, ATPG pattern generation and validation.
• Execute Zero-Delay and SDF timing simulations.
• Debug simulations using VCS, NCSim, or Xcelium.

Skills

BSCAN

MBIST

SCAN

ATPG

Simulation methodologies

STA/PD collaboration

Digital ASIC/VLSI

Compression architecture

Cross-functional mentoring

Education

B.E./B.Tech in Electronics & Communication

M.E./M.Tech in VLSI / Microelectronics

Tools

Siemens Tessent

Synopsys

Cadence

Job description

Job Description: DFT Engineer (Senior / Manager)

Role: DFT Engineer / Lead

Location: Bangalore, India (Work from office / Hybrid depending on project)

Experience: 3 to 15 Years

Employment Type: Full-Time, Permanent

Company - Our client is an established, specialized semiconductor engineering services firm delivering cutting-edge VLSI and SoC design solutions to global tier-1 chipmakers and fabless giants. Built on nearly a decade of domain expertise and solid financial stability, the organization specializes in end-to-end turnkey DFT execution down to advanced 3nm technology nodes. They offer engineers deep technical ownership across multi-EDA tool ecosystems and full-lifecycle silicon execution.

Role Overview

We are looking for an experienced and hands-on DFT Engineer to work on complex SoC designs and advanced technology nodes. In this role, you will handle architecture, insertion, ATPG pattern generation, simulation, timing constraints, and silicon bring-up activities while collaborating with cross-functional teams.

Key Responsibilities

• Develop and implement SoC-level DFT architecture, including OCC/OPCG insertion, EDT/Compression logic insertion, and clock module handling for scan purposes.
• Perform MBIST insertion, Scan insertion, ATPG pattern generation, and validation.
• Execute both Zero-Delay and SDF Timing Simulations.
• Conduct simulation debugging using GUI mode on industry-standard simulators (VCS, NCSim, or Xcelium).
• Work with fault models including Stuck-at, Transition Delay Faults (TDF), and IDDQ, applying scan test coverage improvement techniques.
• Provide test-mode timing constraints and handoffs to STA and Physical Design (PD) teams.
• Support post-silicon bring-up and/or production activities, including tester debug using shmoo plots and graphs.
• Interface with cross-functional and external stakeholder teams; lead and mentor junior DFT engineers.

Requirements & Technical Skills

• Domain Knowledge: Clear conceptual and practical understanding of BSCAN, MBIST, SCAN, ATPG, and simulation methodologies.
• Tool Expertise: Practical experience in at least one tool ecosystem:
  • Siemens (Tessent)
  • Synopsys
  • Cadence
• Simulators: Hands-on debugging experience with VCS, NCSim, or Xcelium.
• SoC & Flow Exposure: Proven background in digital ASIC/VLSI execution flows, timing closure interaction (STA/PD), and compression architecture.
• Background & Stability: Minimum 2 years of tenure in previous organizations.
• Education: B.E. / B.Tech / M.E. / M.Tech in Electronics & Communication, Electrical, VLSI, Microelectronics, or related engineering fields.
• Notice Period: Immediate to 60 days.