DFT Engineer

Dotch Endeavours; Bengaluru; Hybrid; INR 1,000,000 - 1,800,000; Full time

Job summary

Dotch Endeavours is seeking a skilled DFT Engineer to design for testability, perform scan insertion, ATPG vector generation, and MBIST simulations. You will work with RTL/netlist DFT insertion flows, boundary scan, P1500 and DFT verification across multiple stages of development.

You will collaborate with design, verification and ATE teams, using Mentor, Synopsys and Cadence tools, and will script tasks in Perl and TCL to automate workflows.

Qualifications

• Hands-on experience with scan insertion and ATPG.
• Knowledge of stuck-at and at-speed fault testing.
• Experience with MBIST insertion and simulation.
• Knowledge of boundary scan, TAP controller and P1500.
• Experience in RTL and netlist DFT insertion flows.
• DFT simulation experience, with and without SDF.
• Familiarity with synthesis and formal verification tools.
• Knowledge of DC characterization and TDL generation for ATE.
• Good scripting skills in Perl and TCL.

Responsibilities

• Perform scan insertion and generate ATPG vectors for faults.
• Analyze and improve scan coverage.
• Implement and simulate MBIST.
• Work on boundary scan, TAP controller insertion and P1500.
• Handle RTL-based and netlist DFT insertion flows.
• Perform DFT simulation with and without SDF.
• Collaborate with synthesis and formal verification teams.
• Generate TDL for ATE and assist bring-up with ATE team.
• Use Mentor, Synopsys and Cadence DFT tools.

Skills

Scan insertion

ATPG

MBIST

Boundary scan

P1500

RTL DFT

Netlist DFT insertion

SDF

Synthesis

Formal verification

DC characterization

TDL for ATE

Perl scripting

Tcl scripting

Tools

Mentor DFT tools

Synopsys

Cadence

Job description

DFT Engineer (Design for Testability)

Job Overview

We are looking for a skilled DFT Engineer with hands-on experience in Design for Testability, scan insertion, ATPG, MBIST and DFT verification. The candidate should have practical experience with DFT insertion flows, fault coverage analysis, simulation, and semiconductor test methodologies.

Job Locations:

Bangalore, Kochi, Chennai, Pune

Key Responsibilities

• Perform scan insertion and generate ATPG vectors for stuck-at and at-speed faults.
• Analyze and improve scan coverage.
• Implement and simulate MBIST.
• Work on boundary scan, TAP controller insertion and IEEE 1500 (P1500).
• Handle RTL-based and netlist-based DFT insertion flows.
• Perform DFT simulation with and without SDF.
• Work with synthesis and formal verification tools.
• Perform DC characterization.
• Generate TDL for ATE and collaborate with the ATE team during the bring-up phase.
• Use DFT tools from Mentor, Synopsys and Cadence.
• Apply Perl and TCL scripting to automate DFT tasks.
• Perform Static Timing Analysis, where required.

Required Skills

• Hands-on experience in scan insertion and ATPG.
• Knowledge of stuck-at and at-speed fault testing.
• Experience with MBIST insertion and simulation.
• Knowledge of boundary scan, TAP controller and P1500.
• Experience in RTL and netlist DFT insertion flows.
• DFT simulation experience, with and without SDF.
• Familiarity with synthesis and formal verification tools.
• Knowledge of DC characterization and TDL generation for ATE.
• Good scripting skills in Perl and TCL.

Preferred Skills

• Experience in Static Timing Analysis.
• Exposure to DFT tools from Mentor, Synopsys and Cadence.

Candidates should have practical DFT project experience and the ability to collaborate with design, verification and ATE teams.