DFT Engineer

7Rays Semiconductors; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

7Rays Semiconductors is seeking a DFT/MBIST specialist with hands-on experience in MBIST insertion, scan insertion, ATPG pattern generation and simulations. You will work with industry-standard tools (Cadence, Tessent, Synopsys) and handle zero-delay/SDF timing simulations, debugging in GUI simulators, and fault models like stuck-at, TDF and IDDQ.

Strong cross-functional communication and mentoring are required.

Qualifications

• Clear understanding of BSCAN, MBIST, SCAN, ATPG and Simulation concepts.
• Hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using Cadence/Sie mens Tessent/Synopsys.
• Experience with zero delay and SDF Timing Simulations.
• Good debugging skills using GUI mode of industry standard simulators (VCS, NCSim, Xcelium).
• Familiarity with fault models: stuck-at, TDF, IDDQ; scan test coverage improvement techniques.
• Experience in SoC level DFT with OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan, post-silicon bring-up and production activities.
• Exposure to tester debug using shmoo plots and graphs; test mode timing constraints to STA/PD teams.
• Perl/Tcl scripting knowledge is a plus.
• Strong communication and debugging skills; able to mentor DFT engineers across cross-functional and customer teams.

Skills

BSCAN/MBIST/SCAN/ATPG concepts

MBIST/Scan insertion

ATPG pattern generation

MBIST and BSCAN simulations

Timing simulations (zero delay/SDF)

Debugging with GUI simulators

Fault models: stuck-at, TDF, IDDQ

Scan test coverage improvement

SoC level DFT, OCC/OPCG insertion

EDT/Compression logic insertion

Clock module handling for scan

Test mode timing constraints for STA/P

Perl/Tcl scripting

Cross-functional communication

Mentoring DFT engineers

Tools

Cadence

Siemens Tessent

Synopsys

VCS

NCSim

Xcelium

Job description

• The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.
• Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.
• Candidate must have worked on zero delay as well as SDF Timing Simulations.
• Must have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
• The candidate should have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.
• Candidate should have worked in SoC level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and /or production activities with exposure to Tester debug usings shmoo plots and graphs.
• The candidate should have experience of providing test mode timing constraints to STA and PD teams.
• Additional knowledge of perl/tcl scripting will be an advantage.
• Good communication skills and debugging skills are a must to have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.