DFT (Design for Testability) Lead

7Rays Semiconductors; Telangana; On-site; INR 1,800,000 - 3,600,000; Full time

Job summary

7Rays Semiconductors in Telangana, India is seeking an experienced DFT Engineer to strengthen our VLSI test capabilities. You will implement MBIST and scan chains, run ATPG patterns, and perform timing simulations to ensure robust SoC testability.

You will work with Cadence/Synopsys tool suites, debug using GUI simulators, and mentor junior DFT engineers while interfacing with cross-functional teams and customers on test strategy and validation.

Qualifications

• Clear understanding of BSCAN, MBIST, SCAN, ATPG and Simulation concepts.
• Hands-on MBIST insertion, Scan Insertion, ATPG pattern generation and simulations.
• Experience with zero delay and SDF Timing Simulations.
• Good debugging using GUI mode of VCS, NCSim or Xcelium.
• Knowledge of fault models like stuck-at, TDF, IDDQ and scan test coverage.
• Experience in SoC level DFT with OCC/OPCG insertion and clock module handling for scan.
• Experience providing test mode timing constraints to STA and PD teams.
• Perl/Tcl scripting knowledge is a plus.
• Strong communication and debugging skills, mentoring DFT engineers.

Responsibilities

• Lead cross-functional teams and mentor DFT engineers.
• Design and implement MBIST/SCAN strategies for SoC testability.
• Generate ATPG patterns and validate with simulations.
• Collaborate with customers on test requirements and timing constraints.

Skills

MBIST insertion

Scan Insertion

ATPG pattern generation

DFT concepts

Bug debugging

SoC DFT exposure

Clock module handling

Perl / TCL scripting

Cross-functional communication

Tools

Cadence Tessent

Siemens Tessent

Synopsys

VCS / NCSim / Xcelium

Job description

At 7Rays Semiconductors (https://7rayssemi.com/), we provide end-to-end VLSI design solutions to help our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using the latest technologies and methodologies

We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a proven track record of successful projects, we are committed to excellence and innovation in semiconductor design.

Role -

• The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.
• Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.
• He/she must have worked on zero delay as well as SDF Timing Simulations.
• Must have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
• The candidate should have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.
• He/she should have worked in SoC level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and /or production activities with exposure to Tester debug usings shmoo plots and graphs.
• The candidate should have experience of providing test mode timing constraints to STA and PD teams.
• Additional knowledge of perl/tcl scripting will be an advantage.
• Good communication skills and debugging skills are a must to have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.