Dft Design Engineer

Leadic Design; Hyderabad; On-site; INR 900,000 - 1,500,000; Full time

Job summary

LeadIC is seeking an experienced verification engineer to contribute hands-on expertise in scan insertion and ATPG within a cutting-edge semiconductor design team in India.

Knowledge of MBIST and JTAG is required, and proficiency with Synopsys DC, Cadence, and Tessent ATPG is highly valued.

Qualifications

• Hands-on experience with Scan insertion and ATPG is required.
• Knowledge of MBIST and JTAG is essential.
• Tools: Synopsys DC, Cadence, Tessent ATPG are used in this role.

Tools

Scan insertion

ATPG

MBIST

JTAG

Synopsys DC

Cadence

Tessent ATPG

Job description

Job Overview

Hands‑on experience required in Scan insertion and ATPG (Expert/must).

Should have knowledge of MBIST and JTAG.

Tools: Synopsys DC, Cadence, Tessent ATPG.

Skills highlighted with “” are preferred key skills.

Company

Founded in 2018, LeadIC has evolved into a trusted partner for global semiconductor companies, supporting the complete chip development lifecycle with deep technical capability. Engineering teams are located across India, Germany, and Canada.