Lead DFT Engineer

Simaxtech; Bengaluru; On-site; INR 2,000,000 - 3,200,000; Full time

Job summary

Simaxtech in Bangalore seeks an experienced DFT Engineer to lead design-for-test implementation for complex SoCs. You will oversee scan insertion, ATPG, test compression, MBIST/LBIST, and JTAG, collaborating with RTL, verification, and physical teams to maximise test coverage and manufacturability.

The role requires 8+ years in DFT, strong Verilog/SystemVerilog skills, and proficiency with EDA tools such as Tessent, DFT Compiler/Test MAX, and Modus.

Qualifications

• Strong understanding of DFT concepts, scan architecture, ATPG, MBIST, LBIST, and JTAG.
• Hands-on experience with industry-standard EDA tools such as Tessent, DFT Compiler/Test MAX, or Cadence Modus.
• Good knowledge of Verilog/SystemVerilog and digital design fundamentals.

Responsibilities

• Develop and implement DFT architecture for complex SoC/ASIC designs.
• Perform scan insertion, scan stitching, and scan chain verification.
• Generate ATPG patterns for stuck-at, transition, and path delay faults.
• Implement and validate test compression, MBIST, and boundary scan (JTAG).
• Analyze and improve test coverage while minimizing pattern count.
• Debug DFT-related issues during simulation, silicon bring-up, and production testing.
• Collaborate with RTL, verification, and physical design teams to ensure seamless DFT integration.
• Prepare DFT documentation, test plans, and support manufacturing test activities.

Skills

DFT concepts

Scan architecture

ATPG

MBIST

LBIST

JTAG

Verilog/SystemVerilog

Debugging

Problem solving

Scripting languages

Tools

Tessent (Siemens)

DFT Compiler/Test MAX (Synopsys)

Modus (Cadence)

Job description

Role & responsibilities

Position: DFT Engineer
Experience: 8+ Years
Location: Bangalore

Job Summary

We are looking for an experienced DFT Engineer to join our VLSI team. The ideal candidate should have strong expertise in Design for Test (DFT) implementation, scan insertion, ATPG, compression techniques, and test architecture for complex SoCs. The candidate will work closely with design, verification, and physical design teams to ensure high test coverage and manufacturability.

Key Responsibilities

• Develop and implement DFT architecture for complex SoC/ASIC designs.
• Perform scan insertion, scan stitching, and scan chain verification.
• Generate ATPG patterns for stuck-at, transition, and path delay faults.
• Implement and validate test compression, MBIST, and boundary scan (JTAG).
• Analyze and improve test coverage while minimizing pattern count.
• Debug DFT-related issues during simulation, silicon bring-up, and production testing.
• Collaborate with RTL, verification, and physical design teams to ensure seamless DFT integration.
• Prepare DFT documentation, test plans, and support manufacturing test activities.

Required Skills

• Strong understanding of DFT concepts, scan architecture, ATPG, MBIST, LBIST, and JTAG.
• Hands-on experience with industry-standard EDA tools such as Siemens Tessent, Synopsys DFT Compiler/Test MAX, or Cadence Modus.
• Good knowledge of Verilog/System Verilog and digital design fundamentals.
• Experience with fault simulation, test coverage analysis, and pattern generation.
• Familiarity with scripting languages such as Tcl, Perl, or Python.
• Understanding of ASIC design flow from RTL to GDSII.
• Strong debugging, analytical, and problem-solving skills.