DFT Engineer

Neurealm; Pune District; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Neurealm is seeking a detail-oriented DFT/ASIC verification engineer to contribute hands-on in inserting scan chains, generating ATPG vectors, and improving scan coverage. The role involves MBIST insertion, boundary scan, and P1500 tap controller work, with experience across RTL and netlist insertion flows, DFT simulations, and SDF-aware verification.

The candidate will engage with synthesis, formal verification, and DC characteristics, and collaborate with ATE teams during bring-up.

Qualifications

• Hands-on experience in inserting scan and generating ATPG vectors for test patterns.
• Stuck-At and At-Speed Fault analysis with emphasis on improving scan coverage.
• MBIST insertion and simulation experience for memory BIST flows.
• Boundary Scan knowledge including inserting tap controller and P1500.
• RTL-based and netlist-based insertion flows.
• DFT simulation with/without SDF; synthesis and formal verification exposure.
• DC characteristics and device-level parameterization experience.

Responsibilities

• Inserting scan chains and generating ATPG vectors for testability.
• Analyzing and improving scan coverage for high fault coverage.
• Performing MBIST insertion and simulation tasks.
• Working with Boundary Scan, P1500, and test access mechanisms.
• Executing RTL-based and netlist-based insertion flows.
• Carrying out DFT simulations and coordinating with synthesis/tools teams.
• Preparing documentation and scripts for DFT flows and ATE bring-up.

Skills

ATPG vectors

Stuck-At faults

MBIST

Boundary Scan

RTL-based insertion

Netlist-based insertion

DFT simulation

Synthesis

Formal verification

DC Characteristics

TDL for ATE

ATE bring-up

DFT tools (Mentor/Synopsys/Cadence)

Perl scripting

TCL scripting

Static Timing Analysis

Education

BE/ME or BTech /MTech

Tools

none

Job description

• Hands on experience in Inserting Scan and generating ATPG vectors for
• Stuck-At and At-Speed Faults. In-depth experience in analysing and improving scan coverage
• Hands on experience in MBIST (insertion and simulation)
• Experience in Boundary Scan, inserting tap controller and P1500
• Experience in RTL based and netlist-based insertion flows
• Experience in DFT simulation with and without SDF Experience in Synthesis and formal verification tools
• Experience in characterization (DC Characteristics)
• Experience in generating TDL for ATE and working closely with ATE team during bring-up phase
• Good exposure to DFT tools from Mentor, Synopsys and Cadence
• Good scripting know-how in Perl and TCL
• Experience in Static Timing analysis preferred

Educational Qualification: BE/ME or BTech /MTech