Design and Verification Engineer

SignOff semiconductors; Bengaluru; Vor Ort; INR 1.200.000 - 1.800.000; Vollzeit

Zusammenfassung

SignOff semiconductors is seeking an experienced verification engineer to lead end-to-end ASIC/SoC/IP verification activities, define plans, methodologies, and sign-off criteria. You will develop and review UVM/SystemVerilog based verification environments, drive verification execution, debugging, regression, and coverage closure, and collaborate with customers and design teams to ensure on-time delivery.

The role requires a strong RTL/digital design foundation and hands-on expertise with GLS,

Qualifikationen

• 4-9 years of ASIC/SoC/IP functional verification experience.
• Strong hands-on expertise in GLS, SystemVerilog and UVM.
• Experience developing testbenches, sequences, scoreboards, monitors, drivers, and coverage models.
• Good understanding of constrained-random and coverage-driven verification methodologies.
• Experience with simulation, debugging, regression, coverage analysis, verification planning, and sign-off.
• Strong knowledge of RTL design and digital design concepts.
• Experience with AMBA AXI/AHB/APB, PCIe, Ethernet, USB, DDR.

Aufgaben

• End-to-end ASIC/SoC/IP verification activities.
• Define verification plans, methodologies, and sign-off criteria.
• Develop and review UVM/SystemVerilog-based verification environments.
• Drive verification execution, debugging, regression, and coverage closure.
• Collaborate with customers, design teams, and stakeholders to ensure successful project delivery.
• Ensure quality execution and delivery within project timelines.

Kenntnisse

GLS

SystemVerilog

UVM

Testbenches

Constrained-random

Coverage-driven verification

RTL design fundamentals

Digital design concepts

Ausbildung

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, VLSI, or related field

Tools

AMBA AXI/AHB/APB

PCIe

Ethernet

USB

DDR

Jobbeschreibung

Key Responsibilities

• End-to-end ASIC/SoC/IP verification activities.
• Define verification plans, methodologies, and sign-off criteria.
• Develop and review UVM/SystemVerilog-based verification environments.
• Drive verification execution, debugging, regression, and coverage closure.
• Collaborate with customers, design teams, and stakeholders to ensure successful project delivery.
• Ensure quality execution and delivery within project timelines.

Requirements

Required Skills

• 4-9 years of ASIC/SoC/IP Functional Verification experience.
• Strong hands-on expertise in GLS , SystemVerilog and UVM.
• Experience developing testbenches, sequences, scoreboards, monitors, drivers, and coverage models.
• Good understanding of constrained-random and coverage-driven verification methodologies.
• Experience with simulation, debugging, regression, coverage analysis, verification planning, and sign-off.
• Strong knowledge of RTL design and digital design concepts.
• Experience with one or more protocols:
  • AMBA AXI/AHB/APB
  • PCIe
  • Ethernet
  • USB
  • DDR

Preferred Skills

• Python, Perl, or C/C++ scripting.
• Experience working with global customers and distributed teams.

Education

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, VLSI, or a related field.