ASIC/SoC Design Verification Engineer

PQAngels Technologies Pvt. Ltd; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Benefits offered by this job

Health Insurance

Performance-Based Incentives

Professional Growth & Career Advance

Job summary

PQAngels Technologies Pvt. Ltd.

is a product engineering company delivering end-to-end engineering solutions across the silicon-to-software stack. We partner with semiconductor companies, OEMs, and technology-driven enterprises to accelerate product development through expertise in ASIC/SoC Design, Design Verification, Physical Design, Embedded Systems, Firmware, Software Engineering, AI, Cloud, and DevOps.

Qualifications

• UTM/UVML-based verification focus
• Reusable verification environments
• Coverage closure and sign-off requirements

Responsibilities

• Develop verification plans based on architecture and design specs.
• Design and maintain reusable UVM-based verification environments.
• Create scalable testbenches for IP, subsystem and SoC verification.
• Develop directed, constrained-random, and regression test cases.
• Implement SystemVerilog Assertions (SVA) for verification.
• Drive functional and coverage closure.
• Debug using waveform analysis and root-cause analysis.
• Execute regression suites and analyze failures.
• Verify protocols such as PCIe, DDR, AXI, USB, Ethernet, MIPI, CXL, UCIe.
• Collaborate with RTL, DFT, Physical Design, and Architecture teams.
• Mentor junior verification engineers and review deliverables.
• Support verification sign-off activities and milestones.
• Prepare verification reports and coverage metrics.

Skills

UVM

SystemVerilog

SVA

Functional Coverage

Constrained Random Verification

Scoreboards & Functional Checkers

Register Abstraction Layer (RAL)

PCI Express (PCIe)

DDR / LPDDR

AXI

USB

Ethernet

MIPI

CXL

SPI

I2C

UART

Education

Bachelor's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.

Tools

Synopsys VCS

Cadence Xcelium

Siemens QuestaSim

Verdi

DVE

Python

Perl

TCL

Shell Scripting

Job description

PQAngels Technologies Pvt. Ltd | Full time

PQAngels Technologies is a specialized in building high-performance engineering teams for the Post Quantum era of innovation. The company connects cutting-edge technology organizations with highly skilled professionals in Semiconductors, Cloud Computing, and Data Storage ecosystems. PQAngels Technologies focuses on niche engineering roles, enabling clients to innovate faster while offering candidates access to advanced projects and career growth. Applicants can expect to work with leading global tech companies and be part of teams driving next-generation hardware and software solutions.

Job Description

About PQAngels Technologies :
PQAngels Technologies Pvt. Ltd. is a product engineering company delivering end-to-end engineering solutions across the silicon-to-software stack. We partner with semiconductor companies, OEMs, and technology-driven enterprises to accelerate product development through expertise in ASIC/SoC Design, Design Verification, Physical Design, Embedded Systems, Firmware, Software Engineering, AI, Cloud, and DevOps.Role Overview :
We are looking for an experienced Senior Design Verification Engineer with strong expertise in SystemVerilog, UVM, and ASIC/SoC Functional Verification. The ideal candidate should have hands-on experience in developing reusable verification environments, executing complex verification plans, achieving coverage closure, and collaborating with cross-functional design teams throughout the product development lifecycle.
Key Responsibilities :

• Develop comprehensive verification plans based on architecture and design specifications.
  
• Design, develop, and maintain reusable UVM-based verification environments.
  
• Create scalable testbenches and verification components for IP, subsystem, and SoC-level verification.
  
• Develop directed, constrained-random, and regression test cases.
  
• Implement SystemVerilog Assertions (SVA) for protocol and functional verification.
  
• Drive functional, code, and assertion coverage closure.
  
• Perform debugging using waveform analysis and root cause analysis techniques.
  
• Execute regression suites and analyze failures.
  
• Verify complex protocols such as PCIe, DDR, USB, Ethernet, AXI, AHB, APB, MIPI, CXL, or UCIe.
  
• Collaborate closely with RTL, DFT, Physical Design, and Architecture teams.
  
• Participate in design reviews and provide verification feedback.
  
• Mentor junior verification engineers and review verification deliverables.
  
• Support verification sign-off activities and project milestones.
  
• Prepare technical documentation, verification reports, and coverage metrics.
  

Requirements

• Universal Verification Methodology (UVM)
  
• SystemVerilog Assertions (SVA)
  
• Functional Coverage
  
• Constrained Random Verification
  
• Scoreboards & Functional Checkers
  
• Register Abstraction Layer (RAL)
  
• PCI Express (PCIe)
  
• DDR / LPDDR
  
• AXI
  
• USB
  
• Ethernet
  
• MIPI
  
• CXL
  
• SPI
  
• I2C
  
• UART
  

Programming & Verification

• SystemVerilog
  
• Universal Verification Methodology (UVM)
  
• SystemVerilog Assertions (SVA)
  
• Functional Coverage
  
• Constrained Random Verification
  
• Scoreboards & Functional Checkers
  
• Register Abstraction Layer (RAL)
  

Protocol Verification

• PCI Express (PCIe)
  
• DDR / LPDDR
  
• AXI
  
• AHB / APB
  
• USB
  
• Ethernet
  
• MIPI
  
• CXL
  
• UCIe
  
• SPI
  
• I2C
  
• UART
  

EDA Tools

• Synopsys VCS
  
• Cadence Xcelium
  
• Siemens QuestaSim
  
• Verdi
  
• DVE
  

Scripting

• Python
  
• Perl
  
• TCL
  
• Shell Scripting
  

Preferred Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
  
• 4–12 years of experience in ASIC/SoC Design Verification.
  
• Experience verifying complex IPs, subsystems, or full-chip SoCs.
  
• Strong understanding of digital design concepts and RTL (Verilog/SystemVerilog).
  
• Experience with lint, CDC, RDC, and formal verification is an added advantage.
  
• Familiarity with Git, Perforce, or other version control systems.
  
• Experience working in Agile development environments.
  
• Health Insurance
  
• Performance-Based Incentives
  
• Professional Growth & Career Advancement