Design Verification Engineer

MediaTek; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

MediaTek in Bengaluru seeks an experienced ASIC verification engineer to contribute to digital design verification using UVM-based methodologies. You will develop and execute test benches with Verilog/SystemVerilog/SVA, analyze coverage, and collaborate to achieve functional goals.

Proficiency in scripting (Python/Perl/Unix shells) and experience with common verification tools is expected; knowledge of analog mixed-signal principles is a plus.

Qualifications

• Experience in ASIC verification and UVM-based methodologies.
• Hands-on verification with digital design languages and test benches.
• Knowledge of Verilog, SystemVerilog, and SVA for coverage and debug.
• Familiarity with verification tools, scripting, and automation practices.
• Understanding of analog mixed-signal concepts is a plus.

Skills

Quick learner

Strong critical thinking

Creative problem-solving

ASIC verification experience

Power-aware simulations

Scripting & automation

Analog mixed-signal knowledge

Programming: C/C++/SystemC

Tools

UVM

Verilog

SystemVerilog

SystemVerilog Assertions (SVA)

Unix/Linux shell

Perl

Python

Makefile

Perforce/ClearCase

SystemC

Job description

• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, Digital Design and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals,
• Good ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, etc.
• Power-aware simulations and gate level simulations is a plus
• Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
• Familiar with programming languages: C, C++, and/or SystemC is a plus.