Design Verification Engineer

Dignifyd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Dignifyd in Bengaluru is seeking an experienced Design Verification Engineer to join our ASIC/SoC verification team. You will design and maintain SystemVerilog/UVM based verification environments to validate complex IPs and designs.

The ideal candidate has 6–10 years hands-on experience, strong debugging skills, and a deep understanding of Ethernet and PCIe protocols, functional coverage, and regression testing.

Qualifications

• 6–10 years of hands-on verification experience in DV roles.
• Strong SystemVerilog and UVM proficiency for verification environments.
• Experience verifying Ethernet and PCIe protocols.
• Ability to develop test plans, test scenarios and verification strategies.
• Hands-on with testbenches, sequences, drivers, monitors and scoreboards.
• Experience with functional coverage, assertions and regression testing.

Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments.
• Create test plans, test scenarios, test cases, and verification strategies.
• Develop UVM testbenches, sequences, drivers, monitors, scoreboards, and coverage.
• Perform functional, regression, and corner-case verification of designs.
• Debug RTL, simulation failures, protocol issues, and coverage gaps.
• Analyze simulation results and collaborate with RTL, Architecture and Validation teams.

Skills

SystemVerilog

UVM

Ethernet protocol

PCIe protocol

Debugging

Testbench development

Job description

We are looking for an experienced Design Verification Engineer with 6–10 years of hands‑on experience in SystemVerilog and UVM‑based verification. The ideal candidate will have strong experience verifying complex ASIC/SoC/IP designs and good knowledge of high‑speed communication protocols, particularly Ethernet and PCIe.

Key Responsibilities:

• Develop and maintain SystemVerilog/UVM‑based verification environments.
• Create test plans, test scenarios, test cases, and verification strategies.
• Develop UVM testbenches, sequences, drivers, monitors, scoreboards, and functional coverage.
• Perform functional, regression, and corner‑case verification of IP/SoC designs.
• Debug RTL, simulation failures, protocol issues, and coverage gaps.
• Analyze simulation results and work closely with RTL Design, Architecture, and Validation teams.

Required Technical Skills:

• 6–10 years of hands‑on experience in Design Verification.
• Strong programming/verification experience in SystemVerilog.
• Strong hands‑on experience with UVM.
• Good understanding of Verilog/SystemVerilog simulation and debugging.
• Minimum 2+ years of experience with Ethernet and/or PCIe protocol verification.
• Good understanding of Ethernet MAC concepts and/or PCIe architecture/protocol.
• Experience with functional coverage, assertions, constrained‑random verification, and regression testing.