Senior Design Verification Engineer

BrainChip; Hyderabad; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

BrainChip in Hyderabad is seeking a Senior Design Verification Engineer for on-site work to verify ASIC designs and architectures, with a focus on functional verification, debugging and meeting customer requirements.

The role involves developing verification plans, building test benches and reusable models, collaborating with cross-functional teams to enhance verification processes.

Qualifications

• B.Tech. with 1–3 years or M.Tech. with 0–2 years of relevant experience.
• Experience in verification flow understanding of complex IPs/units and sub-systems.
• Verification experience using random stimulus with functional coverage and assertion-based verification.
• Expertise in Verilog.
• Knowledge in System Verilog or similar HVL.
• Familiarity with verification methodologies like UVM and exposure to industry standard verification tools for simulation and debug.
• Experience with System Verilog Assertion (SVA) a plus.
• Experience with Perl, Python or other scripting language is a plus
• Experience with Industry Standard protocols like I2C/SPI/GPIO/AXI/APB/AHB is a plus

Responsibilities

• Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies.
• Expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
• Come up tests and verification infrastructure for complex IPs/sub-systems by using the test plan document.
• Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Skills

Verilog

SystemVerilog

UVM

SVA

Perl

Python

I2C

SPI

AXI

AHB

Education

B.Tech. in Engineering

M.Tech. (optional)

Job description

This is a full-time on-site role for a Senior Design Verification Engineer located in Hyderabad. The Design Verification Engineer will be responsible for performing Functional verification. Key tasks include debugging, ensuring designs meet customer requirements, documenting verification plans, and collaborating with cross-functional teams to improve the verification process.

Responsibilities

• Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies.
• Expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
• Come up tests and verification infrastructure for complex IPs/sub-systems by using the test plan document.
• Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Qualifications

• B.Tech. with 1-3 years/ M.Tech. with 0-2 years of relevant experience.
• Experience in verification flow understanding of complex IPs/units and sub-systems.
• Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies.
• Expertise in Verilog.
• Knowledge in System Verilog or similar HVL.
• Familiarity with verification methodologies like UVM and exposure to industry standard verification tools for simulation and debug.
• Experience with System Verilog Assertion (SVA) a plus.
• Experience with Perl, Python or other scripting language is a plus
• Experience with Industry Standard protocols like I2C/SPI/GPIO/AXI/APB/AHB is a plus