Functional Verification Lead

Mulya Technologies; Bengaluru; On-site; INR 2,500,000 - 3,500,000; Full time

Job summary

Mulya Technologies in Bengaluru is looking for an ASIC Functional Verification Lead to oversee the development of verification environments and test cases for SOCs and ASICs. The ideal candidate will have over 15 years of extensive experience in functional verification, including debugging and developing test plans.

This role requires strong leadership abilities to guide teams while ensuring high-quality design standards are maintained. Candidates should possess deep knowledge of ASIC verification methodologies and protocols.

Qualifications

• 15+ years of experience in functional verification of processors or ASICs.
• Experience with 3rd‑party IP blocks such as DDR, Ethernet, PCIe.
• Self-starter, ready to move quickly to keep the design moving forward.

Responsibilities

• Lead the development of the verification environment and testbenches.
• Debug and fix logic design issues, delivering quality design.
• Ensure coverage criteria is met with the development team.

Skills

Functional verification tools

Debugging logic design issues

Leading a team

Test plans and strategies

Object-oriented programming

Scripting languages

Continuous integration and DevOps

Education

Bachelor's Degree

Tools

UVM

SystemVerilog

Verilog

VHDL

Git

Linux/Unix

Job description

About the Company

We design and operate the systems that keep the world running. From high‑resilience mainframes and hybrid cloud platforms to networking, automation, and site reliability, our teams ensure performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future‑ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, we provide the opportunities to build expertise and shape the infrastructure that drives progress.

About the Role

As an ASIC Functional Verification Lead, you will work on SOC or ASICs used in servers and other customers. You’ll lead the development of the verification environment, testbenches, and writing test cases. Your responsibilities include:

• Developing skills in functional verification tools and methodologies.
• Working with design teams and other key stakeholders to debug and fix logic design issues, delivering a quality design.
• Working with the development team to ensure coverage criteria is met.
• Leading a young team by defining and delivering the best quality chips.

Required Education

• Bachelor's Degree

Required Technical and Professional Expertise

• 15+ years of experience in functional verification of processors or ASICs.
• Minimum 15+ years of experience in any of the following: experience with 3rd‑party IP blocks such as DDR, Ethernet, PCIe, USB, NAND, or AXI.
• Self‑starter, ready to move quickly to keep the design moving forward.
• IO subsystem knowledge, including protocols like PCIe, CXL, DDR, Flash, Ethernet, AXI, AHB, ACE, ACE‑lite, and SoC fabric verification.
• Gate‑level simulation and emulation; track record in leading a team.
• Clock‑domain crossing and reset‑domain crossing verification.
• Knowledge of functional verification methodology—UVM/OVM/SystemVerilog/SystemC—and HDLs such as Verilog and VHDL.
• Developed test plans and test strategies for IP/unit/block‑level verification; good object‑oriented programming skills in C/C++ and scripting languages like Python/Perl.
• Experience across multiple verification levels (unit/element/sub‑system/system level).
• Development experience on Linux/Unix environments, Git repositories, and a good understanding of continuous integration and DevOps workflows.
• Exposure to developing testbench environments, writing complex test scenarios, debugging, and triaging failures.

Preferred Technical and Professional Experience

• Stress testing and ability to identify corner‑case scenarios.
• Knowledge of high‑speed SERDES and PHY verification.
• Good understanding of computer system architecture and microarchitecture.
• Knowledge in IP integration and SoC‑level verification.
• Exposure to automation.