Job Posting Title Senior Staff ASIC Design Verification Engineer

MaxLinear, Inc.; Bengaluru; Presencial; INR 1.200.000 - 2.000.000; Jornada completa

Descripción de la vacante

MaxLinear, Inc. is seeking a Senior Staff ASIC Design Verification Engineer in Bengaluru, India. This role involves leading complex verification activities at the IP, Subsystem, and SoC levels. Candidates should have 8–12 years of hands-on ASIC Design Verification experience, strong capabilities in UVM-based verification, and proficiency in SystemVerilog, UVM, and C/C++. The position offers an opportunity to apply AI-assisted workflows to enhance verification quality and productivity.

Formación

• 8–12 years of hands-on ASIC Design Verification experience.
• Strong experience in IP, Subsystem, and SoC verification, preferably in networking or packet-processing domains.
• Solid experience building and maintaining scalable UVM-based verification environments.

Responsabilidades

• Lead and execute verification activities at the IP, Subsystem, and SoC levels.
• Define verification test plans and contribute to overall verification strategy.
• Develop, enhance, and maintain reusable UVM-based verification components and environments.

Conocimientos

SystemVerilog

UVM

Verilog

C/C++

Python

Perl

Shell scripting

Educación

Bachelor’s or Master’s degree in Electronic Engineering

Descripción del empleo

Responsibilities

We are looking for a Senior Staff ASIC Design Verification Engineer to lead complex verification execution and contribute significantly to IP, Subsystem, and SoC-level verification. This role requires strong hands‑on expertise, ownership of verification deliverables, and the ability to apply advanced methodologies and AI‑assisted workflows to ensure quality and on‑time tape‑out. You will focus on:

• Lead and execute verification activities at the IP, Subsystem, and SoC levels
• Define verification test plans and contribute to overall verification strategy
• Develop, enhance, and maintain reusable UVM‑based verification components and environments
• Drive functional and code coverage closure and debug complex verification issues
• Own key verification deliverables from development through sign‑off
• Apply AI‑assisted techniques to improve debug speed, test generation, coverage analysis, and regression efficiency
• Analyze verification metrics and continuously improve verification quality and productivity
• Collaborate closely with design, architecture, validation, and cross‑functional teams
• Contribute to verification best practices, automation initiatives, and process improvements

Qualifications

• Bachelor’s or Master’s degree in Electronic Engineering or a related field
• 8–12 years of hands‑on ASIC Design Verification experience
• Strong experience in IP, Subsystem, and SoC verification, preferably in networking or packet‑processing domains
• Solid experience building and maintaining scalable UVM‑based verification environments
• Strong proficiency in:
  • SystemVerilog, UVM, Verilog
  • C/C++
• Good understanding of verification methodologies, including directed and constrained‑random testing, coverage‑driven verification, and gate‑level simulations
• Experience with Linux/Unix environments and scripting languages such as Python, Perl, or Shell
• Working knowledge of high‑speed protocols such as Ethernet, PCIe, USB 3.0, and SERDES
• Exposure to SystemC and DSP is a plus
• Experience leveraging AI‑assisted verification tools or workflows is highly desirable
• Strong problem‑solving skills, attention to detail, and effective communication abilities