Staff Verification Design Engineer

Sierra Wireless; Hyderabad; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Sierra Wireless in Hyderabad, India, seeks a verification engineer to perform block and chip-level verification across RTL, gate-level and AMS, with emphasis on SystemVerilog and UVM. You will run digital/mixed-signal simulations, develop verification plans, and drive regressions to ensure tape-out readiness.

The role requires 3+ years in semiconductors, an MS in EE/CS/CE, and strong scripting in Python/Perl.

Qualifications

• 3+ years experience in semiconductor industry
• M.S. in EE/CS/CE or higher
• Hands-on experience with System Verilog as High-level Verification Language and UVM implementation
• Debugging digital simulation in both RTL and gate-level netlist
• Scripting experience in Python or Perl
• Clear understanding of ASIC design flow
• Solid analytical, synthesis and problem solving skills
• Independent, self-motivated, rigorous, team player and able to follow through

Responsibilities

• Perform block and chip-level verification in RTL, gate-level and AMS.
• Run digital/mixed-signal simulations as well as formal verification.
• Work closely with the design team to create verification strategy and detailed verification plan.
• Develop tests, run regressions and monitor coverage to ensure tape-out quality.
• Participate in design or project reviews and support these with verification perspective and schedule/priority assessment.
• Support post-silicon bring-up and debug, for bench validation as well as automated test equipment (ATE) testing.
• Improve verification scalability and portability from project to project by environment enhancement and tools automation.

Skills

SystemVerilog

UVM

RTL verification

Gate-level verification

AMS verification

Python

Perl

Debugging

VHDL

ASIC design flow

Education

M.S. in EE/CS/CE or higher

Tools

Python

Perl

Job description

Responsibilities:

• Perform block and chip-level verification in register-transfer level (RTL), gate-level and analog/mixed-signal (AMS).

• Run digital/mixed-signal simulations as well as formal verification.

• Work closely with the design team to create verification strategy and detailed verification plan.

• Develop tests, run regressions and monitor coverage to ensure tape-out quality.

• Participate in design or project reviews and support these with verification perspective and schedule/priority assessment.

• Support post-silicon bring-up and debug, for bench validation as well as automated test equipment (ATE) testing.

• Improve verification scalability and portability from project to project by environment enhancement and tools automation.

Minimum Qualifications:

• 3+ years experience in semiconductor industry

• M.S. in EE/CS/CE or higher

• Hands-on experience with System Verilog as High-level Verification Language and UVM implementation.

• Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and system level.

• Scripting experience in Python or Perl.

• Clear understanding of ASIC design flow

• Solid analytical, synthesis and problem solving skills

• Independent, self-motivated, rigorous, team player and able to follow through

• Excellent verbal and written communication skills

Desired Qualifications

• Experience of setting up UVM verification environment from scratch

• Familiarity with VHDL or System Verilog RNM

• Automation of verification flow with Python/Perl in industrial setting

• Analog behavioral model development/verification experience