Get more replies from employers
Send a job-specific resume in minutes.
UST is seeking a senior candidate with 4–8 years of hands-on Analog and Mixed-Signal layout experience for high-end HSIO/GPIO and DDR I/O work. The role requires strong knowledge of custom layout techniques and exposure to leading nodes like 2nm, 3nm, and 5nm, along with proficiency in Cadence Virtuoso and Calibre.
Ideal applicants will have a proven track record on tape-outs, solid problem-solving skills, and clear communication for cross-functional collaboration in a fast-paced semiconductor
Required Skills 4–8 years of hands-on experience in Analog, Mixed-Signal, and I/O Layout design. Strong exposure to advanced TSMC and Samsung technology nodes (2nm, 3nm, and 5nm). Proven experience in designing: High-Speed I/O (HSIO) General Purpose I/O (GPIO) DDR I/O (DDRIO) Strong knowledge of custom layout techniques, including device matching, common centroid, shielding, guard rings, and routing optimization. Experience with DRC, LVS, ERC, PEX, and layout closure. Hands-on experience with Cadence Virtuoso and industry-standard custom layout tools and flows. Good understanding of semiconductor manufacturing processes and physical design constraints. Preferred Qualifications Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field. Experience with successful tape-outs on advanced technology nodes. Strong analytical, debugging, and problem-solving skills. Excellent communication and collaboration skills.