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UST in Bengaluru, India, seeks an Analog Layout Engineer to develop full custom layouts for cutting-edge technology nodes. The role requires strong knowledge of layout electrical parameters and quick learning to build IPs and macros with CAD tools.
Experience with Virtuoso and Calibre is preferred; familiarity with reliability concepts is a plus. You will handle sub-cells/leaf cells, perform chip‑level integration, physical verification and electrical closure, and contribute to analog, digital
The role involves execution in the field of full custom layouts in cutting edge technology nodes. It requires good layout electrical parameter knowledge and quick learning capabilities.
Candidate should be able to handle sub‑cells/leaf cells needed to build IP/macro using CAD tools, perform chip‑level integration, physical verification, and electrical closure. Candidate will be exposed to various other fields of custom layout, including custom layout expertise in lower‑technology digital, analog, and mixed‑signal layout. Good understanding of reliability concepts and layout electrical parameters is essential.
This position is for Analog Layout Engineers with experience in custom block layout such as PLL, Bandgap, ADC, DAC, etc., and familiarity with Virtuoso, Calibre, DRC, and LVS. Requires TSMC 3nm and 2nm 3‑way NDA in place. 3–5 years of experience required.