Associate III - VLSI AL SVP

UST

Bengaluru

On-site

INR 1,500,000 - 2,200,000

Full time

14 days+

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Job summary

UST in Bengaluru is seeking Analog Layout Engineers to execute full custom layouts for cutting-edge technology nodes. You will handle sub cells/leaf cells to build IP/macros using CAD tools, and perform chip-level integration, physical verification and electrical closure.

Candidate should have expertise in Analog/Digital/Mixed-signal layout, reliability concepts, and strong knowledge of layout electrical parameters.

Qualifications

  • The role involves execution in the field of full custom layouts in cutting edge technology nodes.
  • Candidate should be able to handle sub cells/leaf cells to build IP/macros using CAD tools.
  • Chip level integration, physical verification and electricals closure.
  • Analog Layout Engineers with experience in custom block layout like PLL, Bandgap, ADC, DAC.

Responsibilities

  • Execute full custom layouts for analog/mixed-signal blocks.
  • Work with CAD tools to create sub cells and macros for IPs.
  • Perform layout verification and electrical closure activities.
  • Contribute to reliability considerations in layout designs.

Skills

vlsi design
analog design
layout engineering
virtuoso
cad design
calibre
macros
resumate

Tools

Virtuoso
Calibre

Job description

Role Description
  • The role involves execution in the field of full custom layouts in cutting edge technology nodes.
  • It will require a good layout electrical parameter knowledge along with quick learning capabilities.
  • Candidate should be able to handle sub cells/leaf cells that are needed to build IP/macro using CAD tools.
  • Chip level integration, physical verification and electricals closure.
  • Candidate will be exposed/experienced to various other fields of custom layout.
  • Custom layout expertise in lower technology.
  • Digital, Analog and mixed signal layout.
  • Good understanding of reliability concepts.
  • Good understating of layout electrical parameters and closure.
  • This is for Analog Layout Engineers having exp in custom block layout like PLL, Bandgap, ADC, DAC etc. and Virtuoso, Calibre, DRC, LVS.
  • Requires TSMC 3nm and 2nm 3-way NDA in place.
  • 3-5 years of experience required.
Skill
  • vlsi design
  • resumate
  • calibre
  • macros
  • layout engineering
  • cad design
  • virtuoso
Skills
  • vlsi design
  • analog design
  • layout engineering
  • virtuoso
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