Associate II - VLSI PDK

UST; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

UST seeks a proficient layout engineer in Bengaluru to work on Cadence-based layout and mixed-signal blocks. You will handle AMS, charge pumps, IOs, and reference generators, collaborating with design leads and CAD teams to meet project milestones.

Strong knowledge of layout concepts, DFM/PDK, and scripting (PERL/SKILL) is valued. The role focuses on timely delivery within a fast-paced semiconductor environment in India.

Qualifications

• Experience with Cadence platform and layout concepts.
• Knowledge of Matching, shielding, Symmetry, ESD, latch-up, DFM/PDK and rule-set development.
• Experience with high-speed IO, charge pumps, regulators, semi-custom blocks.
• Scripting knowledge a plus: PERL and SKILL.

Responsibilities

• Handle block layouts like AMS, Charge Pumps, I/Os, Reference generator.
• Interact with project lead (design and layout) and CAD for various requirements.
• Complete all tasks as defined by the leads on time.

Skills

Analog Layout

Analog Mixed-Signal

Cadence

Charge Pumps

Job description

Role Description

Requirements: Experience in Cadence Platform Knowledge of layout concepts like Matching, shielding, Symmetry, ESD, latch‑up, Reliability and DFM PDK and rule‑set development understanding Working experience in blocks like high-speed IO, Charge pumps, Regulators, semi‑custom blocks etc. Scripting knowledge a plus: PERL and SKILL Good communication (written and verbal) and interpersonal skills Excellent working ability with circuit design and layout methodology development teams Excellent problem‑solving skills Responsibilities: Handling block layouts like AMS, Charge Pumps, I/O’s, Reference generator Interaction with project lead (design and layout) and CAD for various requirements Complete all the tasks as defined by the leads on time.

Role Description

Requirements: Experience in Cadence Platform Knowledge of layout concepts like Matching, shielding, Symmetry, ESD, latch‑up, Reliability and DFM PDK and rule‑set development understanding Working experience in blocks like high-speed IO, Charge pumps, Regulators, semi‑custom blocks etc. Scripting knowledge a plus: PERL and SKILL Good communication (written and verbal) and interpersonal skills Excellent working ability with circuit design and layout methodology development teams Excellent problem‑solving skills Responsibilities: Handling block layouts like AMS, Charge Pumps, I/O’s, Reference generator Interaction with project lead (design and layout) and CAD for various requirements Complete all the tasks as defined by the leads on time.

Skills

Analog Layout, Analog Mixed‑Signal, Cadence, Charge Pumps