Associate III - VLSI PDK

UST; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

UST in Bengaluru is seeking an experienced IC layout engineer to work on Cadence-based layout design for high‑speed analog blocks such as I/O, charge pumps and regulators. You will collaborate with circuit designers and layout teams to implement robust layout methodologies and PDK rule sets.

Strong communication and problem solving are essential, and scripting knowledge in PERL or SKILL is a plus. The role expects delivery of tasks on time and adherence to project deadlines.

Qualifications

• Experience with Cadence platform and layout methodology.
• Knowledge of high-speed IO, charge pumps, regulators and semi-custom blocks.
• Scripting knowledge in PERL and SKILL is a plus.

Responsibilities

• Handling block layouts like AMS, Charge Pumps, I/O’s, Reference generator.
• Interaction with project lead (design and layout) and CAD for various requirements.
• Complete all tasks as defined by the leads on time.

Skills

Analog Layout

Analog Mixed-Signal

High speed IO

Charge Pumps

Tools

Cadence

PERL

SKILL

Job description

Role Description

Requirements: Experience in Cadence Platform Knowledge of layout concepts like Matching, shielding, Symmetry, ESD, latch-up, Reliability and DFM PDK and rule-set development understanding Working experience in blocks like high speed IO, Charge pumps, Regulators, semi-custom blocks etc. Scripting knowledge a plus: PERL and SKILL Good communication (written and verbal) and interpersonal skills Excellent working ability with circuit design and layout methodology development teams Excellent problem-solving skills Responsibilities: Handling block layouts like AMS, Charge Pumps, I/O’s, Reference generator Interaction with project lead (design and layout) and CAD for various requirements Complete all the tasks as defined by the leads on time.

Role Description

Requirements: Experience in Cadence Platform Knowledge of layout concepts like Matching, shielding, Symmetry, ESD, latch-up, Reliability and DFM PDK and rule-set development understanding Working experience in blocks like high speed IO, Charge pumps, Regulators, semi-custom blocks etc. Scripting knowledge a plus: PERL and SKILL Good communication (written and verbal) and interpersonal skills Excellent working ability with circuit design and layout methodology development teams Excellent problem-solving skills Responsibilities: Handling block layouts like AMS, Charge Pumps, I/O’s, Reference generator Interaction with project lead (design and layout) and CAD for various requirements Complete all the tasks as defined by the leads on time.

Skills

Analog Layout, Analog Mixed-Signal, Cadence, Charge Pumps