Associate II - VLSI - PD SVP

UST; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

UST in Bengaluru is seeking an experienced ASIC/SoC physical design engineer to join our advanced technology team. You will work on synthesis, floorplanning, placement, CTS, routing, and timing closure using industry-standard flows.

You will drive PPA optimization, perform DRC/LVS sign-off, and apply UPF/CPF flows for multi-volt, low-power designs on 16nm and 5nm nodes. Strong problem-solving skills and ISO 26262 experience are a plus.

Qualifications

• 3-5 years of experience in ASIC/SoC physical design.
• Strong knowledge of EDA tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, PrimeTime, Voltus).
• Expertise in timing analysis, signal integrity, and power analysis.
• Experience with advanced nodes (e.g., 16nm, 5nm).
• Familiarity with DFT insertion, low-power design, and multi-clock domain handling.
• Good understanding of physical verification and manufacturing sign-off.
• Strong problem-solving and debugging skills.
• Experience in Automotive or Industrial MPU/MCU SoCs (preferred for safety-critical designs and ISO 26262).

Responsibilities

• Execute floorplanning, placement, CTS, routing, and timing closure.
• Drive power, performance, and area (PPA) optimization.
• Conduct physical verification (DRC/LVS) and sign-off checks.
• Work on multi-voltage, low-power design techniques and UPF/CPF flows.
• Support ECO implementation and tape-out activities.

Skills

VLSI design

Physical design

Low power design

Floor planning

Electrical engineering

Education

Bachelor's/Master's in Electrical Engineering, Electronics or related

Tools

Synopsys ICC2/Fusion Compiler

Cadence Innovus

PrimeTime

Voltus

Job description

Role Description

The ideal candidate will have strong expertise in ASIC/SoC physical design flows, including synthesis, floorplanning, placement, PNR, clock tree synthesis, routing, timing closure, and sign-off. This role requires hands-on experience with industry-standard EDA tools and a deep understanding of advanced technology nodes.

Key Responsibilities

• Execute floorplanning, placement, CTS, routing, and timing closure.
• Drive power, performance, and area (PPA) optimization.
• Conduct physical verification (DRC/LVS) and sign-off checks.
• Work on multi-voltage, low-power design techniques and UPF/CPF flows.
• Support ECO implementation and tape-out activities.

Required Skills & Qualifications

• 3-5 years of experience in ASIC/SoC physical design.
• Strong knowledge of EDA tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, PrimeTime, Voltus, etc.).
• Expertise in timing analysis, signal integrity, and power analysis.
• Experience with advanced nodes (e.g., 16nm, 5nm).
• Familiarity with DFT insertion, low-power design, and multi-clock domain handling.
• Good understanding of physical verification and manufacturing sign-off.
• Strong problem-solving and debugging skills.
• Experience in working on Automotive or Industrial MPU/MCU SoCs (preferred for safety-critical designs and compliance with standards like ISO 26262).

Preferred Qualifications

• Experience with high-performance SoCs or complex IP blocks.
• Knowledge of EM/IR analysis and reliability checks.

Education

• Familiarity with scripting languages (Tcl, Perl, Python) for flow automation. Education Bachelor s or Master s degree in Electrical Engineering, Electronics, or related field.

Skills

vlsi design,physical design,low power design,floor planning,electrical engineering