Analog Layout Engineer

Lakshya Software Technologies Pvt. Ltd.; Hyderabad; On-site; INR 800,000 - 1,200,000; Full time

Job summary

Lakshya Software Technologies Pvt. Ltd. in India seeks an experienced analog layout engineer to design and integrate critical analog and mixed-signal blocks for high-performance CMOS processes.

You will perform layout verification, ensure on-time delivery of block-level layouts, and collaborate with global engineering teams to drive project success. Strong Cadence VLE/VXL and Calibre LVS/DRC skills are essential.

Qualifications

• 3-5 years of experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Calibre DRC/LVS.
• Hands-on experience designing analog layout blocks (Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current sources).
• Strong understanding of analog layout fundamentals (matching, EM, latch-up, coupling, cross-talk, IR-drop, parasitics).
• Understanding layout effects on circuit speed, capacitance, power and area.
• Ability to understand constraints and deliver high-quality layouts.
• Excellent verbal and written communication skills.

Responsibilities

• Design and develop critical analog/custom layout blocks and integrate at full-chip level.
• Perform layout verification and quality checks.
• Ensure on-time delivery of block-level layouts with acceptable quality.
• Collaborate with cross-functional teams across India, US, and Japan to assure project success.

Skills

Analog layout design

Layout verification

Communication

Problem solving

Tools

Cadence VLE/VXL

Calibre DRC/LVS

Scripting/Automation

Job description

• Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Contribute to effective project-management.
• Effectively communicating with engineering teams in the India, US, and Japan to assure the success of the layout project.

Qualification/Requirements

• 3-5 year experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must.
• Should have hands on experience of Critical Analog Layout design of blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current
• Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
• Ability to understand design constraints and implement high-quality layouts.
• Excellent command and problem-solving skills in Physical layout verification.
• Good understanding of basic active and passive devices such as R,L, C and MOSFETs
• Scripting and automation experience is good to have but not mandatory.
• Excellent verbal and written communication skills.