ASIC / SoC Design Verification Engineer

Pqangels Technologies; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

PQAngels Technologies is seeking experienced Design Verification Engineers to work on SoC/IP verification projects using SystemVerilog and UVM.

You will develop verification plans, create reusable UVM environments, and perform functional coverage analysis, SVA, and protocol verification. You will collaborate with RTL, physical design, and cross-functional teams to deliver sign-off-ready results.

Qualifications

• Hands-on experience in SystemVerilog and UVM.
• Experience with SVA and functional coverage.
• IP/SoC and protocol verification experience.
• Strong debugging, analytical and problem-solving skills.
• Good communication and stakeholder management.

Responsibilities

• Develop verification plans and test strategies.
• Develop and maintain reusable UVM verification environments.
• Create testbenches, test cases, sequences, scoreboards, monitors and coverage models.
• Perform functional coverage analysis and coverage closure.
• Develop and debug SystemVerilog Assertions (SVA).
• Execute simulations and regressions using industry-standard EDA tools.
• Debug failures and perform root cause analysis.
• Perform IP/SoC and protocol verification.
• Collaborate with RTL, Physical Design, and other cross-functional teams.
• Participate in customer interactions and technical discussions.
• Prepare verification reports and documentation.
• Support verification signoff and quality deliverables.

Skills

SystemVerilog

UVM

SVA / SystemVerilog Assertions

Functional Coverage

Protocol Verification

Python / TCL

SoC/IP Verification

Testbench Development

Regression & Debugging

Tools

VCS

Xcelium

QuestaSim

Verdi

Job description

Job Description

PQAngels Technologies is looking for experienced Design Verification Engineers with strong expertise in SystemVerilog and UVM to work on SoC/IP verification projects.

The ideal candidate should have hands-on experience in UVM testbench development, functional coverage, SVA, protocol verification, debugging, regression, and verification signoff.

Key Responsibilities

• Develop verification plans and test strategies.
• Develop and maintain reusable UVM verification environments.
• Create testbenches, test cases, sequences, scoreboards, monitors, and coverage models.
• Perform functional coverage analysis and coverage closure.
• Develop and debug SystemVerilog Assertions (SVA).
• Execute simulations and regressions using industry-standard EDA tools.
• Debug failures and perform root cause analysis.
• Perform IP/SoC and protocol verification.
• Collaborate with RTL, Physical Design, and other cross-functional teams.
• Participate in customer interactions and technical discussions.
• Prepare verification reports and documentation.
• Support verification signoff and quality deliverables.

Mandatory Skills

• SystemVerilog
• UVM
• SVA / SystemVerilog Assertions
• Functional Coverage
• Protocol Verification
• Python / TCL
• SoC/IP Verification
• Testbench Development
• Regression & Debugging

EDA Tools

• Synopsys VCS
• Cadence Xcelium
• Siemens QuestaSim
• Synopsys Verdi

Preferred Candidate

• 4-11 years of experience in Design Verification / VLSI Verification.
• Strong hands-on experience with SystemVerilog and UVM.
• Experience in SoC/IP verification and protocol verification.
• Strong debugging, analytical, and problem-solving skills.
• Good communication and stakeholder management skills.
• Ability to work with global customers and cross-functional teams.