Senior Design Verification Engineer : Bangalore

Incise Infotech; Bengaluru; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

Incise Infotech in Bengaluru seeks an experienced Verification Engineer with strong SystemVerilog, UVM, and Ethernet verification skills to join our semiconductor/VLSI team. You will design and execute verification plans for complex digital/IP/SoC designs, and build scalable environments using SystemVerilog and UVM.

The role includes creating testbenches, test cases, assertions, coverage models, and performing protocol verification focused on Ethernet designs, while debugging simulations and

Qualifications

• Experience with SystemVerilog/UVM verification of digital/IP/SoC designs.
• Hands-on Ethernet protocol verification.
• Experience building testbenches, checkers, and coverage models.
• Strong debugging and regression experience.
• Familiarity with SV/UVM simulators and scripting.

Responsibilities

• Develop and execute verification plans for complex digital/IP/SoC designs.
• Build scalable verification environments using SystemVerilog and UVM.
• Create testbenches, test cases, assertions, checkers, and coverage models.
• Perform protocol verification with emphasis on Ethernet-based designs.
• Debug simulation failures and collaborate with design/architecture teams.
• Analyze functional/code coverage and drive verification closure.
• Participate in regression execution and automation activities.
• Support bring-up and validation activities as required.

Skills

SystemVerilog

UVM

Ethernet protocols

Verification env development

Digital design concepts

Debugging

Scripting

SoC/IP verification

AXI/APB/AHB

Education

Bachelor's/Master's in Electronics/ECE/VLSI

Tools

VCS

Xcelium

Questa

Job description

We are looking for an experienced Verification Engineer with strong expertise in SystemVerilog, UVM, and Ethernet protocol verification to join our growing semiconductor/VLSI team.

Key Responsibilities

• Develop and execute verification plans for complex digital/IP/SoC designs.
• Build scalable and reusable verification environments using SystemVerilog and UVM methodology.
• Create testbenches, test cases, assertions, checkers, and coverage models.
• Perform protocol verification with strong focus on Ethernet-based designs.
• Debug simulation failures and collaborate closely with design and architecture teams.
• Analyze functional/code coverage and ensure verification closure.
• Participate in regression execution and automation activities.
• Support bring-up and validation activities when required.

Mandatory Skills

• Strong hands-on experience in SystemVerilog (SV) and UVM
• Good understanding of Ethernet protocols
• Experience in verification environment development and debugging
• Strong knowledge of digital design and verification concepts
• Experience with simulators like VCS/Xcelium/Questa
• Understanding of assertions, coverage-driven verification, and scripting

Preferred Skills

• Experience in SoC/IP verification
• Knowledge of protocols such as AXI/APB/AHB is an added advantage
• Familiarity with Python/Perl/Shell scripting
• Strong debugging and problem-solving skills

Qualification

• Bachelors or Masters degree in Electronics/ECE/VLSI or related field

Interested Candidates