Design Verification Engineer

Prodapt Solutions; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Prodapt Solutions is seeking a skilled Design Verification Engineer to join our team and verify complex SoC architectures for high-quality silicon. You will develop verification plans and build testbenches using SystemVerilog/UVM, writing tests, sequences, and assertions.

You will perform functional, regression, and coverage-driven verification, debug issues with design teams, and analyze coverage to improve test quality. Joining between 0-15 days is expected.

Qualifications

• 3–8 years of experience in Design Verification.
• Develop and execute verification plans for SoC/IP level designs.
• Build and maintain testbenches using System Verilog/UVM.
• Write test cases, sequences, and assertions to validate functionality.
• Perform functional, regression, and coverage-driven verification.
• Debug failures and work closely with design teams to resolve issues.
• Analyze coverage metrics and improve test quality.
• Participate in reviews of design and verification environments.

Responsibilities

• Develop and execute verification plans for SoC/IP level designs.
• Build and maintain testbenches using System Verilog/UVM.
• Write test cases, sequences, and assertions to validate functionality.
• Perform functional, regression, and coverage-driven verification.
• Debug failures and work closely with design teams to resolve issues.
• Analyze coverage metrics and improve test quality.
• Participate in reviews of design and verification environments.

Skills

SystemVerilog

UVM

SoC architecture

Digital design concepts

Simulation tools (VCS, Xcelium)

AMBA protocols (AXI, AHB, APB)

Scripting (Python/Perl/Shell)

Education

BE/B.Tech or M.Tech in Electronics, VLSI, or Electrical Engineering

Tools

Synopsys VCS

Cadence Xcelium

Job description

About the Role

We are looking for a skilled Design Verification Engineer to join our team and work on next-generation semiconductor designs. You will be responsible for verifying complex System-on-Chip (SoC) architectures to ensure high-quality, reliable silicon.

Key Responsibilities

• 3 - 8 years of experience in Design Verification


• Develop and execute verification plans for SoC/IP level designs


• Build and maintain testbenches using System Verilog/UVM


• Write test cases, sequences, and assertions to validate functionality


• Perform functional, regression, and coverage-driven verification


• Debug failures and work closely with design teams to resolve issues


• Analyze coverage metrics and improve test quality


• Participate in reviews of design and verification environments

Required Skills

• Strong experience in System Verilog and UVM (Universal Verification Methodology)


• Good understanding of SoC architecture and digital design concepts


• Experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium)


• Knowledge of debugging using waveforms and logs


• Familiarity with protocols like AMBA (AXI, AHB, APB)


• Scripting knowledge (Python/Perl/Shell) is a plus

Preferred Qualifications

• Experience with low-power verification


• Exposure to formal verification tools


• Understanding of embedded systems or firmware interaction

Education

• B.E./B.Tech or M.Tech in Electronics, VLSI, or Electrical Engineering.

Note - Candidates are expected to join between 0 - 15 days.