Senior Design Verification Engineer

Eximietas Design; Ahmedabad District, Bengaluru; On-site; INR 3,500,000 - 4,500,000; Full time

Job summary

Eximietas Design seeks an experienced Senior Design Verification Engineer to lead verification across complex SoC projects in India. You will drive verification planning, testbench development, and cross-functional collaboration across architect, design, and pre/post-silicon teams.

The role requires strong UVM, SystemVerilog, and industry tool proficiency with a track record in IP/SoC verification; familiarity with PCIe, Ethernet, CXL, MIPI, DDR, HBM, and peripheral interfaces is a plus.

Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field.
• Master's degree in Computer Science, Electrical/Electronics Engineering, or a related field.
• PhD in Computer Science, Electrical/Electronics Engineering, or a related field.
• 310 years of hands-on experience in SoC Design Verification.
• Expertise in UVM (Universal Verification Methodology) and SystemVerilog.
• Prior experience working on IP-level and SoC-level verification projects.
• Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs).
• Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, and MIPI protocols.
• Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols.
• Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF.
• Proficiency in scripting languages such as Shell, Makefile, and Perl.
• Strong understanding of processor-based SoC verification, including Native, Verilog, SystemVerilog, and UVM mixed environments.
• Experience with C-SystemVerilog handshake and writing C test cases for boot-up verification.
• Excellent problem-solving, analytical, and debugging skills.

Responsibilities

• Lead and manage Design Verification efforts for complex projects, ensuring the successful execution of verification plans.
• Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SoCs, including I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR, and HBM.
• Conduct Gate-level simulations and power-aware verification using Xprop and UPF.
• Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams.
• Analyze and implement SystemVerilog assertions and coverage (code, toggle, functional).
• Provide mentorship and technical guidance to junior verification engineers.
• Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment.
• Ensure verification signoff criteria are met and documentation is comprehensive.
• Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines.
• Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies.
• Experience with verification tools from Synopsys and Cadence, including VCS and Xsim.
• Integration of third-party VIPs (Verification IP) from Synopsys and Cadence.

Skills

UVM expertise

SystemVerilog

Shell scripting

Problem solving

VIP integration

Education

Bachelor's degree in CS/EE

Master's degree in CS/EE

PhD in CS/EE

Tools

VCS

Xsim

waveform analyzers

Synopsys/Cadence VIPs

Job description

Job Overview

We are seeking an experienced and highly skilled Senior Design Verification Engineer with 310 years of hands-on experience in Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System-on-Chip designs.

Location: Bangalore / Ahmedabad / Pune / Hyderabad

Job Description

• Lead and manage Design Verification efforts for complex projects, ensuring the successful execution of verification plans.
• Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SoCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR, and HBM.
• Conduct Gate-level simulations and power-aware verification using Xprop and UPF.
• Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams.
• Analyze and implement SystemVerilog assertions and coverage (code, toggle, functional).
• Provide mentorship and technical guidance to junior verification engineers.
• Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment.
• Ensure verification signoff criteria are met and documentation is comprehensive.
• Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines.
• Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies.
• Experience with verification tools from Synopsys and Cadence, including VCS and Xsim.
• Integration of third-party VIPs (Verification IP) from Synopsys and Cadence.

Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field. or
• Master's degree in Computer Science, Electrical/Electronics Engineering, or a related field. or
• PhD in Computer Science, Electrical/Electronics Engineering, or a related field.
• 310 years of hands-on experience in SoC Design Verification.
• Expertise in UVM (Universal Verification Methodology) and SystemVerilog.
• Prior experience working on IP-level and SoC-level verification projects.
• Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs).
• Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, and MIPI protocols.
• Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols.
• Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF.
• Proficiency in scripting languages such as Shell, Makefile, and Perl.
• Strong understanding of processor-based SoC verification, including Native, Verilog, SystemVerilog, and UVM mixed environments.
• Experience with C-SystemVerilog handshake and writing C test cases for boot-up verification.
• Excellent problem-solving, analytical, and debugging skills.